nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-24 10:34:43 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: vgpu: create hal vgpu unit

Browse Source 
File vgpu_fifo_gv11b.c contained syncpoint related implementation
specific to gv11b. Move the implementations to a new file in
hal directory for vgpu hal/vgpu/sync/syncpt_cmdbuf_gv11b_vgpu.c.
Also move function vgpu_gv11b_init_fifo_setup_hw() to a new
file in hal directory for vgpu hal/vgpu/fifo/fifo_gv11b_vgpu.c.

Add a new yaml file nvgpu-hal-vgpu.yaml that contains vgpu
specific hal files. Update arch yaml to reflect the above changes.

Jira GVSCI-994

Change-Id: Ie33614473d5fd3fcd624c70709b109c4e45725ef
Signed-off-by: Aparna Das <aparnad@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2138390
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Nirav Patel <nipatel@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Aparna Das
2019-06-18 14:41:57 -07:00
committed by mobile promotions
parent 8380e7bde6
commit 21c7a00f18
10 changed files with 122 additions and 33 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
drivers/gpu/nvgpu/Makefile
View File

@@ -597,7 +597,6 @@ nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \
common/vgpu/fifo/engines_vgpu.o \
common/vgpu/fifo/preempt_vgpu.o \
common/vgpu/fifo/runlist_vgpu.o \
common/vgpu/fifo/vgpu_fifo_gv11b.o \
common/vgpu/fifo/ramfc_vgpu.o \
common/vgpu/fifo/userd_vgpu.o \
common/vgpu/ce_vgpu.o \
@@ -615,7 +614,9 @@ nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \
common/vgpu/gr/fecs_trace_vgpu.o \
common/vgpu/gp10b/vgpu_hal_gp10b.o \
common/vgpu/gv11b/vgpu_gv11b.o \
common/vgpu/gv11b/vgpu_hal_gv11b.o
common/vgpu/gv11b/vgpu_hal_gv11b.o \
hal/vgpu/fifo/fifo_gv11b_vgpu.o \
hal/vgpu/sync/syncpt_cmdbuf_gv11b_vgpu.o
nvgpu-$(CONFIG_NVGPU_CYCLESTATS) += \
common/perf/cyclestats_snapshot.o \

5
drivers/gpu/nvgpu/Makefile.sources
View File

@@ -438,7 +438,6 @@ srcs += common/vgpu/init/init_vgpu.c \
common/vgpu/fifo/engines_vgpu.c \
common/vgpu/fifo/preempt_vgpu.c \
common/vgpu/fifo/runlist_vgpu.c \
common/vgpu/fifo/vgpu_fifo_gv11b.c \
common/vgpu/fifo/ramfc_vgpu.c \
common/vgpu/fifo/userd_vgpu.c \
common/vgpu/perf/perf_vgpu.c \
@@ -454,7 +453,9 @@ srcs += common/vgpu/init/init_vgpu.c \
common/vgpu/ce_vgpu.c \
common/vgpu/gv11b/vgpu_gv11b.c \
common/vgpu/gv11b/vgpu_hal_gv11b.c \
common/vgpu/gp10b/vgpu_hal_gp10b.c
common/vgpu/gp10b/vgpu_hal_gp10b.c \
hal/vgpu/fifo/fifo_gv11b_vgpu.c \
hal/vgpu/sync/syncpt_cmdbuf_gv11b_vgpu.c
ifeq ($(CONFIG_NVGPU_COMPRESSION),1)
srcs += common/vgpu/cbc/cbc_vgpu.c

12
drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c
View File

@@ -84,8 +84,11 @@
#include "hal/sync/sema_cmdbuf_gv11b.h"
#include "hal/init/hal_gv11b.h"
#include "hal/init/hal_gv11b_litter.h"
#include "hal/fifo/channel_gv11b.h"
#include "hal/vgpu/fifo/fifo_gv11b_vgpu.h"
#include "hal/vgpu/sync/syncpt_cmdbuf_gv11b_vgpu.h"
#include "common/clk_arb/clk_arb_gp10b.h"
#include <nvgpu/gk20a.h>
@@ -112,7 +115,6 @@
#include "common/vgpu/perf/perf_vgpu.h"
#include "common/vgpu/gr/fecs_trace_vgpu.h"
#include "common/vgpu/perf/cyclestats_snapshot_vgpu.h"
#include "common/vgpu/fifo/vgpu_fifo_gv11b.h"
#include "common/vgpu/ptimer/ptimer_vgpu.h"
#include "vgpu_hal_gv11b.h"
@@ -567,8 +569,8 @@ static const struct gpu_ops vgpu_gv11b_ops = {
.sync = {
#ifdef CONFIG_TEGRA_GK20A_NVHOST
.syncpt = {
.alloc_buf = vgpu_gv11b_fifo_alloc_buf,
.free_buf = vgpu_gv11b_fifo_free_buf,
.alloc_buf = vgpu_gv11b_syncpt_alloc_buf,
.free_buf = vgpu_gv11b_syncpt_free_buf,
.add_wait_cmd = gv11b_syncpt_add_wait_cmd,
.get_wait_cmd_size =
gv11b_syncpt_get_wait_cmd_size,
@@ -577,7 +579,7 @@ static const struct gpu_ops vgpu_gv11b_ops = {
.add_incr_cmd = gv11b_syncpt_add_incr_cmd,
.get_incr_cmd_size =
gv11b_syncpt_get_incr_cmd_size,
.get_sync_ro_map = vgpu_gv11b_fifo_get_sync_ro_map,
.get_sync_ro_map = vgpu_gv11b_syncpt_get_sync_ro_map,
},
#endif
.sema = {

36
drivers/gpu/nvgpu/hal/vgpu/fifo/fifo_gv11b_vgpu.c Normal file
View File

@@ -0,0 +1,36 @@
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/gk20a.h>
#include <nvgpu/vgpu/vgpu.h>
#include "fifo_gv11b_vgpu.h"
int vgpu_gv11b_init_fifo_setup_hw(struct gk20a *g)
{
struct nvgpu_fifo *f = &g->fifo;
struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
f->max_subctx_count = priv->constants.max_subctx_count;
return 0;
}

30
drivers/gpu/nvgpu/hal/vgpu/fifo/fifo_gv11b_vgpu.h Normal file
View File

@@ -0,0 +1,30 @@
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_FIFO_GV11B_VGPU_H
#define NVGPU_FIFO_GV11B_VGPU_H
struct gk20a;
int vgpu_gv11b_init_fifo_setup_hw(struct gk20a *g);
#endif

18
drivers/gpu/nvgpu/common/vgpu/fifo/vgpu_fifo_gv11b.c → drivers/gpu/nvgpu/hal/vgpu/sync/syncpt_cmdbuf_gv11b_vgpu.c
View File

@@ -27,7 +27,7 @@
#include <nvgpu/vgpu/tegra_vgpu.h>
#include <nvgpu/channel.h>
#include "common/vgpu/fifo/vgpu_fifo_gv11b.h"
#include "syncpt_cmdbuf_gv11b_vgpu.h"
#include "common/vgpu/ivc/comm_vgpu.h"
#ifdef CONFIG_TEGRA_GK20A_NVHOST
@@ -73,7 +73,7 @@ static int set_syncpt_ro_map_gpu_va_locked(struct vm_gk20a *vm)
return 0;
}
int vgpu_gv11b_fifo_alloc_buf(struct nvgpu_channel *c,
int vgpu_gv11b_syncpt_alloc_buf(struct nvgpu_channel *c,
u32 syncpt_id, struct nvgpu_mem *syncpt_buf)
{
int err;
@@ -120,7 +120,7 @@ int vgpu_gv11b_fifo_alloc_buf(struct nvgpu_channel *c,
return 0;
}
void vgpu_gv11b_fifo_free_buf(struct nvgpu_channel *c,
void vgpu_gv11b_syncpt_free_buf(struct nvgpu_channel *c,
struct nvgpu_mem *syncpt_buf)
{
nvgpu_gmmu_unmap(c->vm, syncpt_buf, syncpt_buf->gpu_va);
@@ -128,7 +128,7 @@ void vgpu_gv11b_fifo_free_buf(struct nvgpu_channel *c,
nvgpu_dma_free(c->g, syncpt_buf);
}
int vgpu_gv11b_fifo_get_sync_ro_map(struct vm_gk20a *vm,
int vgpu_gv11b_syncpt_get_sync_ro_map(struct vm_gk20a *vm,
u64 *base_gpuva, u32 *sync_size)
{
struct gk20a *g = gk20a_from_vm(vm);
@@ -147,13 +147,3 @@ int vgpu_gv11b_fifo_get_sync_ro_map(struct vm_gk20a *vm,
return 0;
}
#endif /* CONFIG_TEGRA_GK20A_NVHOST */
int vgpu_gv11b_init_fifo_setup_hw(struct gk20a *g)
{
struct nvgpu_fifo *f = &g->fifo;
struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
f->max_subctx_count = priv->constants.max_subctx_count;
return 0;
}

18
drivers/gpu/nvgpu/common/vgpu/fifo/vgpu_fifo_gv11b.h → drivers/gpu/nvgpu/hal/vgpu/sync/syncpt_cmdbuf_gv11b_vgpu.h
View File

@@ -20,16 +20,20 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_VGPU_FIFO_GV11B_H
#define NVGPU_VGPU_FIFO_GV11B_H
#ifndef NVGPU_SYNCPT_CMDBUF_GV11B_VGPU_H
#define NVGPU_SYNCPT_CMDBUF_GV11B_VGPU_H
#include <nvgpu/types.h>
struct gk20a;
struct nvgpu_channel;
struct nvgpu_mem;
struct vm_gk20a;
int vgpu_gv11b_init_fifo_setup_hw(struct gk20a *g);
int vgpu_gv11b_fifo_alloc_buf(struct nvgpu_channel *c,
int vgpu_gv11b_syncpt_alloc_buf(struct nvgpu_channel *c,
u32 syncpt_id, struct nvgpu_mem *syncpt_buf);
void vgpu_gv11b_fifo_free_buf(struct nvgpu_channel *c,
void vgpu_gv11b_syncpt_free_buf(struct nvgpu_channel *c,
struct nvgpu_mem *syncpt_buf);
int vgpu_gv11b_fifo_get_sync_ro_map(struct vm_gk20a *vm,
int vgpu_gv11b_syncpt_get_sync_ro_map(struct vm_gk20a *vm,
u64 *base_gpuva, u32 *sync_size);
#endif /* NVGPU_VGPU_FIFO_GV11B_H */
#endif /* NVGPU_SYNCPT_CMDBUF_GV11B_VGPU_H */