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gpu: nvgpu: remove kind control capability
Kind is controlled by nvgpu userspace library so related capability flags can be removed from kernel and uapi interface. Jira NVGPU-9832 Bug 4034184 Change-Id: Id2b0a4e1cd784638362116b8d99177467fba998b Signed-off-by: Shashank Singh <shashsingh@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2880391 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: Dinesh T <dt@nvidia.com> Reviewed-by: Ankur Kishore <ankkishore@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
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@@ -1117,7 +1117,6 @@ int nvgpu_init_gpu_characteristics(struct gk20a *g)
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#ifdef CONFIG_NVGPU_BUILD_CONFIGURATION_IS_SAFETY
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nvgpu_set_enabled(g, NVGPU_DRIVER_REDUCED_PROFILE, true);
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#endif
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nvgpu_set_enabled(g, NVGPU_SUPPORT_MAP_DIRECT_KIND_CTRL, true);
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nvgpu_set_enabled(g, NVGPU_SUPPORT_MAP_BUFFER_BATCH, true);
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nvgpu_set_enabled(g, NVGPU_SUPPORT_SPARSE_ALLOCS, true);
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nvgpu_set_enabled(g, NVGPU_SUPPORT_MAP_ACCESS_TYPE, true);
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@@ -74,8 +74,6 @@ struct gk20a;
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"IO coherence support is available"), \
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DEFINE_FLAG(NVGPU_SUPPORT_SPARSE_ALLOCS, \
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"MAP_BUFFER_EX with sparse allocations"), \
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DEFINE_FLAG(NVGPU_SUPPORT_MAP_DIRECT_KIND_CTRL, \
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"Direct PTE kind control is supported (map_buffer_ex)"),\
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DEFINE_FLAG(NVGPU_SUPPORT_MAP_BUFFER_BATCH, \
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"Support batch mapping"), \
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DEFINE_FLAG(NVGPU_SUPPORT_MAPPING_MODIFY, \
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@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2017-2023, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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@@ -52,7 +52,6 @@ struct nvgpu_mapped_buf_priv {
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struct sg_table *sgt;
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};
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/* NVGPU_AS_MAP_BUFFER_FLAGS_DIRECT_KIND_CTRL must be set */
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int nvgpu_vm_map_linux(struct vm_gk20a *vm,
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struct dma_buf *dmabuf,
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u64 map_addr,
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@@ -69,7 +68,6 @@ int nvgpu_vm_map_linux(struct vm_gk20a *vm,
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/*
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* Notes:
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* - Batch may be NULL if map op is not part of a batch.
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* - NVGPU_AS_MAP_BUFFER_FLAGS_DIRECT_KIND_CTRL must be set
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*/
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int nvgpu_vm_map_buffer(struct vm_gk20a *vm,
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int dmabuf_fd,
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@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2017-2022, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2017-2023, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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@@ -349,7 +349,6 @@ struct vm_gk20a {
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#define NVGPU_VM_MAP_CACHEABLE BIT32(1)
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#define NVGPU_VM_MAP_IO_COHERENT BIT32(2)
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#define NVGPU_VM_MAP_UNMAPPED_PTE BIT32(3)
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#define NVGPU_VM_MAP_DIRECT_KIND_CTRL BIT32(4)
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#define NVGPU_VM_MAP_L3_ALLOC BIT32(5)
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#define NVGPU_VM_MAP_PLATFORM_ATOMIC BIT32(6)
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#define NVGPU_VM_MAP_TEGRA_RAW BIT32(7)
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@@ -1,7 +1,7 @@
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/*
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* Color decompression engine support
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*
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* Copyright (c) 2014-2022, NVIDIA Corporation. All rights reserved.
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* Copyright (c) 2014-2023, NVIDIA Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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@@ -1108,8 +1108,7 @@ __releases(&l->cde_app->mutex)
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get_dma_buf(compbits_scatter_buf); /* a ref for nvgpu_vm_map_linux */
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err = nvgpu_vm_map_linux(cde_ctx->vm, compbits_scatter_buf, 0,
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NVGPU_VM_MAP_ACCESS_DEFAULT,
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NVGPU_VM_MAP_CACHEABLE |
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NVGPU_VM_MAP_DIRECT_KIND_CTRL,
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NVGPU_VM_MAP_CACHEABLE,
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gk20a_cde_mapping_page_size(cde_ctx->vm,
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map_offset,
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map_size),
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@@ -1,7 +1,7 @@
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/*
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* GK20A Address Spaces
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*
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* Copyright (c) 2011-2022, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2011-2023, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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@@ -109,13 +109,6 @@ static int gk20a_as_ioctl_map_buffer_ex(
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nvgpu_log_fn(g, " ");
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/* unsupported, direct kind control must be used */
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if (!(args->flags & NVGPU_AS_MAP_BUFFER_FLAGS_DIRECT_KIND_CTRL)) {
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struct gk20a *g = as_share->vm->mm->g;
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nvgpu_log_info(g, "Direct kind control must be requested");
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return -EINVAL;
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}
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return nvgpu_vm_map_buffer(as_share->vm, args->dmabuf_fd,
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&args->offset, args->flags,
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args->page_size,
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@@ -198,15 +191,8 @@ static int gk20a_as_ioctl_map_buffer_batch(
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break;
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}
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if (map_args.flags &
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NVGPU_AS_MAP_BUFFER_FLAGS_DIRECT_KIND_CTRL) {
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compressible_kind = map_args.compr_kind;
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incompressible_kind = map_args.incompr_kind;
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} else {
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/* direct kind control must be used */
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err = -EINVAL;
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break;
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}
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err = nvgpu_vm_map_buffer(
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as_share->vm, map_args.dmabuf_fd,
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@@ -270,8 +270,6 @@ static struct nvgpu_flags_mapping flags_mapping[] = {
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NVGPU_SUPPORT_IO_COHERENCE},
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{NVGPU_GPU_FLAGS_SUPPORT_RESCHEDULE_RUNLIST,
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NVGPU_SUPPORT_RESCHEDULE_RUNLIST},
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{NVGPU_GPU_FLAGS_SUPPORT_MAP_DIRECT_KIND_CTRL,
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NVGPU_SUPPORT_MAP_DIRECT_KIND_CTRL},
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{NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF,
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NVGPU_ECC_ENABLED_SM_LRF},
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{NVGPU_GPU_FLAGS_ECC_ENABLED_SM_SHM,
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@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2017-2022, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2017-2023, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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@@ -72,10 +72,6 @@ static int nvgpu_vm_translate_linux_flags(struct gk20a *g, u32 flags, u32 *out_c
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if (!nvgpu_is_enabled(g, NVGPU_DISABLE_L3_SUPPORT))
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core_flags |= NVGPU_VM_MAP_L3_ALLOC;
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}
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if ((flags & NVGPU_AS_MAP_BUFFER_FLAGS_DIRECT_KIND_CTRL) != 0U) {
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core_flags |= NVGPU_VM_MAP_DIRECT_KIND_CTRL;
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consumed_flags |= NVGPU_AS_MAP_BUFFER_FLAGS_DIRECT_KIND_CTRL;
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}
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if ((flags & NVGPU_AS_MAP_BUFFER_FLAGS_PLATFORM_ATOMIC) != 0U) {
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core_flags |= NVGPU_VM_MAP_PLATFORM_ATOMIC;
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consumed_flags |= NVGPU_AS_MAP_BUFFER_FLAGS_PLATFORM_ATOMIC;
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@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2021-2023, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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@@ -108,7 +108,6 @@ struct nvgpu_as_bind_channel_args {
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#define NVGPU_AS_MAP_BUFFER_FLAGS_UNMAPPED_PTE (1 << 5)
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#define NVGPU_AS_MAP_BUFFER_FLAGS_MAPPABLE_COMPBITS (1 << 6)
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#define NVGPU_AS_MAP_BUFFER_FLAGS_L3_ALLOC (1 << 7)
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#define NVGPU_AS_MAP_BUFFER_FLAGS_DIRECT_KIND_CTRL (1 << 8)
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#define NVGPU_AS_MAP_BUFFER_FLAGS_PLATFORM_ATOMIC (1 << 9)
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#define NVGPU_AS_MAP_BUFFER_FLAGS_TEGRA_RAW (1 << 12)
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@@ -161,11 +160,6 @@ struct nvgpu_as_bind_channel_args {
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*
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* Deprecated.
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*
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* %NVGPU_AS_MAP_BUFFER_FLAGS_DIRECT_KIND_CTRL
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*
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* Set when userspace plans to pass in @compr_kind and @incompr_kind
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* instead of letting the kernel work out kind fields.
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*
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* %NVGPU_AS_MAP_BUFFER_FLAGS_PLATFORM_ATOMIC
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*
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* Specify that a mapping should use platform atomics.
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@@ -178,8 +172,7 @@ struct nvgpu_as_bind_channel_args {
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* @incompr_kind [IN]
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*
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* Specify the compressible and incompressible kinds to be used for the
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* mapping. Requires that %NVGPU_AS_MAP_BUFFER_FLAGS_DIRECT_KIND_CTRL is
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* set in @flags. The kernel will attempt to use @comp_kind and if for
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* mapping. The kernel will attempt to use @comp_kind and if for
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* some reason that is not possible will then fall back to using the
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* @incompr_kind.
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*
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@@ -221,7 +214,6 @@ struct nvgpu_as_bind_channel_args {
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* returned in this field. The field is in bytes.
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*/
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struct nvgpu_as_map_buffer_ex_args {
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/* NVGPU_AS_MAP_BUFFER_FLAGS_DIRECT_KIND_CTRL must be set */
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__u32 flags; /* in/out */
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/*
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@@ -135,8 +135,6 @@ struct nvgpu_gpu_zbc_query_table_args {
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#define NVGPU_GPU_FLAGS_SUPPORT_RESCHEDULE_RUNLIST (1ULL << 21)
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/* subcontexts are available */
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#define NVGPU_GPU_FLAGS_SUPPORT_TSG_SUBCONTEXTS (1ULL << 22)
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/* Direct PTE kind control is supported (map_buffer_ex) */
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#define NVGPU_GPU_FLAGS_SUPPORT_MAP_DIRECT_KIND_CTRL (1ULL << 23)
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/* NVGPU_GPU_IOCTL_SET_DETERMINISTIC_OPTS is available */
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#define NVGPU_GPU_FLAGS_SUPPORT_DETERMINISTIC_OPTS (1ULL << 24)
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/* SCG support is available */
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