diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index ab304f745..0790a7c9e 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -50,6 +50,7 @@ nvgpu-y += \ common/ltc/ltc.o \ common/fbp/fbp.o \ common/cbc/cbc.o \ + common/gr/gr_utils.o \ common/gr/gr.o \ common/gr/gr_intr.o \ common/gr/global_ctx.o \ diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources index 2bcfd9ecb..b43a2f85e 100644 --- a/drivers/gpu/nvgpu/Makefile.sources +++ b/drivers/gpu/nvgpu/Makefile.sources @@ -108,6 +108,7 @@ srcs += common/sim/sim.c \ common/engine_queues/engine_emem_queue.c \ common/engine_queues/engine_fb_queue.c \ common/gr/gr.c \ + common/gr/gr_utils.c \ common/gr/gr_intr.c \ common/gr/global_ctx.c \ common/gr/subctx.c \ diff --git a/drivers/gpu/nvgpu/common/acr/acr_blob_construct_v0.c b/drivers/gpu/nvgpu/common/acr/acr_blob_construct_v0.c index dc5f84e87..e550536b4 100644 --- a/drivers/gpu/nvgpu/common/acr/acr_blob_construct_v0.c +++ b/drivers/gpu/nvgpu/common/acr/acr_blob_construct_v0.c @@ -28,8 +28,8 @@ #include #include #include +#include -#include "common/gr/gr_priv.h" #include "acr_blob_construct_v0.h" #include "acr_falcon_bl.h" #include "acr_wpr.h" @@ -75,8 +75,9 @@ int nvgpu_acr_lsf_fecs_ucode_details_v0(struct gk20a *g, void *lsf_ucode_img) struct lsf_ucode_desc *lsf_desc; struct nvgpu_firmware *fecs_sig; struct flcn_ucode_img *p_img = (struct flcn_ucode_img *)lsf_ucode_img; + struct nvgpu_gr_falcon *gr_falcon = nvgpu_gr_get_falcon_ptr(g); struct nvgpu_ctxsw_ucode_segments *fecs = - nvgpu_gr_falcon_get_fecs_ucode_segments(g->gr->falcon); + nvgpu_gr_falcon_get_fecs_ucode_segments(gr_falcon); int err; fecs_sig = nvgpu_request_firmware(g, GM20B_FECS_UCODE_SIG, 0); @@ -118,7 +119,7 @@ int nvgpu_acr_lsf_fecs_ucode_details_v0(struct gk20a *g, void *lsf_ucode_img) p_img->desc->app_resident_data_offset = fecs->data.offset - fecs->code.offset; p_img->desc->app_resident_data_size = fecs->data.size; - p_img->data = nvgpu_gr_falcon_get_surface_desc_cpu_va(g->gr->falcon); + p_img->data = nvgpu_gr_falcon_get_surface_desc_cpu_va(gr_falcon); p_img->data_size = p_img->desc->image_size; p_img->fw_ver = NULL; @@ -139,8 +140,9 @@ int nvgpu_acr_lsf_gpccs_ucode_details_v0(struct gk20a *g, void *lsf_ucode_img) struct lsf_ucode_desc *lsf_desc; struct nvgpu_firmware *gpccs_sig; struct flcn_ucode_img *p_img = (struct flcn_ucode_img *)lsf_ucode_img; + struct nvgpu_gr_falcon *gr_falcon = nvgpu_gr_get_falcon_ptr(g); struct nvgpu_ctxsw_ucode_segments *gpccs = - nvgpu_gr_falcon_get_gpccs_ucode_segments(g->gr->falcon); + nvgpu_gr_falcon_get_gpccs_ucode_segments(gr_falcon); int err; if (!nvgpu_is_enabled(g, NVGPU_SEC_SECUREGPCCS)) { @@ -187,7 +189,7 @@ int nvgpu_acr_lsf_gpccs_ucode_details_v0(struct gk20a *g, void *lsf_ucode_img) ALIGN(gpccs->code.offset, 256); p_img->desc->app_resident_data_size = ALIGN(gpccs->data.size, 256); p_img->data = (u32 *) - ((u8 *)nvgpu_gr_falcon_get_surface_desc_cpu_va(g->gr->falcon) + + ((u8 *)nvgpu_gr_falcon_get_surface_desc_cpu_va(gr_falcon) + gpccs->boot.offset); p_img->data_size = ALIGN(p_img->desc->image_size, 256); p_img->fw_ver = NULL; @@ -802,6 +804,7 @@ int nvgpu_acr_prepare_ucode_blob_v0(struct gk20a *g) int err = 0; struct ls_flcn_mgr lsfm_l, *plsfm; struct wpr_carveout_info wpr_inf; + struct nvgpu_gr_falcon *gr_falcon = nvgpu_gr_get_falcon_ptr(g); if (g->acr->ucode_blob.cpu_va != NULL) { /* Recovery case, we do not need to form non WPR blob */ @@ -816,7 +819,7 @@ int nvgpu_acr_prepare_ucode_blob_v0(struct gk20a *g) return err; } - err = nvgpu_gr_falcon_init_ctxsw_ucode(g, g->gr->falcon); + err = nvgpu_gr_falcon_init_ctxsw_ucode(g, gr_falcon); if (err != 0) { nvgpu_err(g, "gr_falcon_init_ctxsw_ucode failed err=%d", err); return err; diff --git a/drivers/gpu/nvgpu/common/acr/acr_blob_construct_v1.c b/drivers/gpu/nvgpu/common/acr/acr_blob_construct_v1.c index fdb4356c8..a0878d94c 100644 --- a/drivers/gpu/nvgpu/common/acr/acr_blob_construct_v1.c +++ b/drivers/gpu/nvgpu/common/acr/acr_blob_construct_v1.c @@ -26,7 +26,7 @@ #include #include #include -#include "common/gr/gr_priv.h" +#include #include "acr_blob_construct_v1.h" #include "acr_falcon_bl.h" @@ -82,8 +82,9 @@ int nvgpu_acr_lsf_fecs_ucode_details_v1(struct gk20a *g, void *lsf_ucode_img) struct nvgpu_firmware *fecs_sig = NULL; struct flcn_ucode_img_v1 *p_img = (struct flcn_ucode_img_v1 *)lsf_ucode_img; + struct nvgpu_gr_falcon *gr_falcon = nvgpu_gr_get_falcon_ptr(g); struct nvgpu_ctxsw_ucode_segments *fecs = - nvgpu_gr_falcon_get_fecs_ucode_segments(g->gr->falcon); + nvgpu_gr_falcon_get_fecs_ucode_segments(gr_falcon); int err; switch (ver) { @@ -140,7 +141,7 @@ int nvgpu_acr_lsf_fecs_ucode_details_v1(struct gk20a *g, void *lsf_ucode_img) p_img->desc->app_resident_data_offset = fecs->data.offset - fecs->code.offset; p_img->desc->app_resident_data_size = fecs->data.size; - p_img->data = nvgpu_gr_falcon_get_surface_desc_cpu_va(g->gr->falcon); + p_img->data = nvgpu_gr_falcon_get_surface_desc_cpu_va(gr_falcon); p_img->data_size = p_img->desc->image_size; p_img->fw_ver = NULL; @@ -166,8 +167,9 @@ int nvgpu_acr_lsf_gpccs_ucode_details_v1(struct gk20a *g, void *lsf_ucode_img) struct nvgpu_firmware *gpccs_sig = NULL; struct flcn_ucode_img_v1 *p_img = (struct flcn_ucode_img_v1 *)lsf_ucode_img; + struct nvgpu_gr_falcon *gr_falcon = nvgpu_gr_get_falcon_ptr(g); struct nvgpu_ctxsw_ucode_segments *gpccs = - nvgpu_gr_falcon_get_gpccs_ucode_segments(g->gr->falcon); + nvgpu_gr_falcon_get_gpccs_ucode_segments(gr_falcon); int err; if (!nvgpu_is_enabled(g, NVGPU_SEC_SECUREGPCCS)) { @@ -228,7 +230,7 @@ int nvgpu_acr_lsf_gpccs_ucode_details_v1(struct gk20a *g, void *lsf_ucode_img) ALIGN(gpccs->code.offset, 256); p_img->desc->app_resident_data_size = ALIGN(gpccs->data.size, 256); p_img->data = (u32 *) - ((u8 *)nvgpu_gr_falcon_get_surface_desc_cpu_va(g->gr->falcon) + + ((u8 *)nvgpu_gr_falcon_get_surface_desc_cpu_va(gr_falcon) + gpccs->boot.offset); p_img->data_size = ALIGN(p_img->desc->image_size, 256); p_img->fw_ver = NULL; @@ -930,6 +932,7 @@ int nvgpu_acr_prepare_ucode_blob_v1(struct gk20a *g) int err = 0; struct ls_flcn_mgr_v1 lsfm_l, *plsfm; struct wpr_carveout_info wpr_inf; + struct nvgpu_gr_falcon *gr_falcon = nvgpu_gr_get_falcon_ptr(g); /* Recovery case, we do not need to form non WPR blob of ucodes */ if (g->acr->ucode_blob.cpu_va != NULL) { @@ -938,7 +941,7 @@ int nvgpu_acr_prepare_ucode_blob_v1(struct gk20a *g) plsfm = &lsfm_l; (void) memset((void *)plsfm, 0, sizeof(struct ls_flcn_mgr_v1)); - err = nvgpu_gr_falcon_init_ctxsw_ucode(g, g->gr->falcon); + err = nvgpu_gr_falcon_init_ctxsw_ucode(g, gr_falcon); if (err != 0) { nvgpu_err(g, "gr_falcon_init_ctxsw_ucode failed err=%d", err); return err; diff --git a/drivers/gpu/nvgpu/common/gr/gr_utils.c b/drivers/gpu/nvgpu/common/gr/gr_utils.c new file mode 100644 index 000000000..cdd47092f --- /dev/null +++ b/drivers/gpu/nvgpu/common/gr/gr_utils.c @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include + +#include "gr_priv.h" + +struct nvgpu_gr_falcon *nvgpu_gr_get_falcon_ptr(struct gk20a *g) +{ + return g->gr->falcon; +} + diff --git a/drivers/gpu/nvgpu/include/nvgpu/gr/gr_utils.h b/drivers/gpu/nvgpu/include/nvgpu/gr/gr_utils.h new file mode 100644 index 000000000..5d38ca243 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/gr/gr_utils.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVGPU_GR_UTILS_H +#define NVGPU_GR_UTILS_H + +struct gk20a; +struct nvgpu_gr_falcon; + +struct nvgpu_gr_falcon *nvgpu_gr_get_falcon_ptr(struct gk20a *g); + +#endif /* NVGPU_GR_UTILS_H */