From 21f8b366cd0559882322e00813b3e45b8a81c2e9 Mon Sep 17 00:00:00 2001 From: Scott Long Date: Thu, 23 Jan 2020 11:09:36 -0800 Subject: [PATCH] gpu: nvgpu: fix misra 2.5 violations MISRA Advisory Rule 2.5 states that a project should not contain unused macro declarations. While most of the violations in the nvgpu driver are due to unused macros from hw headers, devinit-related headers, etc. there is a small number that are due to things like: * macros not being used when they could/should be * macros in C files that are really not referenced * CPP build flag mismatches This change eliminates such violations from the following: * replace constants with existing macros in timeout conversion code * wrap nvgpu_gmmu_dbg macro #defines in #ifdef CONFIG_NVGPU_TRACE/#endif * wrap MAX_MC_INTR_REGS #define in #ifdef CONFIG_NVGPU_NON_FUSA/#endif * remove unused FECS_MAILBOX_0_ACK_RESTORE from runlist code * wrap BACKTRACE_MAXSIZE macro with #ifndef _QNX_SOURCE/#endif Jira NVGPU-3178 Change-Id: I2bc72f706d7af3f8e7b062126e8543d0dc8ac250 Signed-off-by: Scott Long Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2284419 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-misra Reviewed-by: svc-mobile-cert Reviewed-by: Vedashree Vidwans Reviewed-by: Sagar Kamble Reviewed-by: Adeel Raza Reviewed-by: mobile promotions Tested-by: mobile promotions GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/common/mm/gmmu/page_table.c | 3 ++- .../nvgpu/hal/fifo/runlist_fifo_gk20a_fusa.c | 4 +--- drivers/gpu/nvgpu/hal/mc/mc_gp10b.h | 2 ++ drivers/gpu/nvgpu/os/posix/bug.c | 2 ++ drivers/gpu/nvgpu/os/posix/timers.c | 18 +++++++++--------- 5 files changed, 16 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/nvgpu/common/mm/gmmu/page_table.c b/drivers/gpu/nvgpu/common/mm/gmmu/page_table.c index 25fda96d2..d375b13ee 100644 --- a/drivers/gpu/nvgpu/common/mm/gmmu/page_table.c +++ b/drivers/gpu/nvgpu/common/mm/gmmu/page_table.c @@ -37,7 +37,7 @@ #include #include - +#ifdef CONFIG_NVGPU_TRACE #define nvgpu_gmmu_dbg(g, attrs, fmt, args...) \ do { \ if ((attrs)->debug) { \ @@ -57,6 +57,7 @@ NVGPU_COV_WHITELIST(false_positive, NVGPU_MISRA(Rule, 14_4), "Bug 2623654") \ } \ NVGPU_COV_WHITELIST(false_positive, NVGPU_MISRA(Rule, 14_4), "Bug 2623654") \ } while (false) +#endif static int pd_allocate(struct vm_gk20a *vm, struct nvgpu_gmmu_pd *pd, diff --git a/drivers/gpu/nvgpu/hal/fifo/runlist_fifo_gk20a_fusa.c b/drivers/gpu/nvgpu/hal/fifo/runlist_fifo_gk20a_fusa.c index 9b8ba07d2..9f3a283ee 100644 --- a/drivers/gpu/nvgpu/hal/fifo/runlist_fifo_gk20a_fusa.c +++ b/drivers/gpu/nvgpu/hal/fifo/runlist_fifo_gk20a_fusa.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2011-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -33,8 +33,6 @@ #include -#define FECS_MAILBOX_0_ACK_RESTORE 0x4U - u32 gk20a_runlist_length_max(struct gk20a *g) { return fifo_eng_runlist_length_max_v(); diff --git a/drivers/gpu/nvgpu/hal/mc/mc_gp10b.h b/drivers/gpu/nvgpu/hal/mc/mc_gp10b.h index 9f88e3572..a29b8f760 100644 --- a/drivers/gpu/nvgpu/hal/mc/mc_gp10b.h +++ b/drivers/gpu/nvgpu/hal/mc/mc_gp10b.h @@ -25,7 +25,9 @@ #include +#ifdef CONFIG_NVGPU_NON_FUSA #define MAX_MC_INTR_REGS 2U +#endif struct gk20a; enum nvgpu_unit; diff --git a/drivers/gpu/nvgpu/os/posix/bug.c b/drivers/gpu/nvgpu/os/posix/bug.c index 24c60b46c..d5f3db53d 100644 --- a/drivers/gpu/nvgpu/os/posix/bug.c +++ b/drivers/gpu/nvgpu/os/posix/bug.c @@ -35,7 +35,9 @@ #include #endif +#ifndef _QNX_SOURCE #define BACKTRACE_MAXSIZE 1024 +#endif struct nvgpu_bug_desc { bool in_use; diff --git a/drivers/gpu/nvgpu/os/posix/timers.c b/drivers/gpu/nvgpu/os/posix/timers.c index 75d9fa498..4e6ec48bb 100644 --- a/drivers/gpu/nvgpu/os/posix/timers.c +++ b/drivers/gpu/nvgpu/os/posix/timers.c @@ -28,7 +28,6 @@ #include #include -#define MSEC_PER_SEC 1000 #define USEC_PER_MSEC 1000 #define NSEC_PER_USEC 1000 #define NSEC_PER_MSEC 1000000 @@ -74,7 +73,7 @@ s64 nvgpu_current_time_us(void) BUG(); } - time_now = nvgpu_safe_mult_s64((s64)now.tv_sec, (s64)1000000); + time_now = nvgpu_safe_mult_s64((s64)now.tv_sec, (s64)NSEC_PER_MSEC); time_now = nvgpu_safe_add_s64(time_now, (s64)now.tv_usec); return time_now; @@ -87,7 +86,7 @@ static s64 get_time_ns(void) (void) clock_gettime(CLOCK_MONOTONIC, &ts); - t_ns = nvgpu_safe_mult_s64(ts.tv_sec, 1000000000); + t_ns = nvgpu_safe_mult_s64(ts.tv_sec, NSEC_PER_SEC); t_ns = nvgpu_safe_add_s64(t_ns, ts.tv_nsec); return t_ns; @@ -151,11 +150,11 @@ static void nvgpu_usleep(unsigned int usecs) t_currentns = get_time_ns(); t_ns = (s64)usecs; - t_ns = nvgpu_safe_mult_s64(t_ns, 1000); + t_ns = nvgpu_safe_mult_s64(t_ns, NSEC_PER_USEC); t_ns = nvgpu_safe_add_s64(t_ns, t_currentns); - rqtp.tv_sec = t_ns / 1000000000; - rqtp.tv_nsec = t_ns % 1000000000; + rqtp.tv_sec = t_ns / NSEC_PER_SEC; + rqtp.tv_nsec = t_ns % NSEC_PER_SEC; (void) clock_nanosleep(CLOCK_MONOTONIC, TIMER_ABSTIME, &rqtp, NULL); } @@ -181,11 +180,12 @@ void nvgpu_msleep(unsigned int msecs) t_currentns = get_time_ns(); t_ns = (s64)msecs; - t_ns = nvgpu_safe_mult_s64(t_ns, 1000000); + t_ns = nvgpu_safe_mult_s64(t_ns, NSEC_PER_MSEC); + t_ns = nvgpu_safe_add_s64(t_ns, t_currentns); - rqtp.tv_sec = t_ns / 1000000000; - rqtp.tv_nsec = t_ns % 1000000000; + rqtp.tv_sec = t_ns / NSEC_PER_SEC; + rqtp.tv_nsec = t_ns % NSEC_PER_SEC; (void) clock_nanosleep(CLOCK_MONOTONIC, TIMER_ABSTIME, &rqtp, NULL); }