diff --git a/drivers/gpu/nvgpu/common/pmu/pmu.c b/drivers/gpu/nvgpu/common/pmu/pmu.c index 1f9701a2f..4c6f2cb7a 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu.c @@ -577,7 +577,7 @@ static void pmu_setup_hw_enable_elpg(struct gk20a *g) if (nvgpu_is_enabled(g, NVGPU_PMU_ZBC_SAVE)) { /* Save zbc table after PMU is initialized. */ pmu->zbc_ready = true; - g->ops.gr.zbc.pmu_save(g, 0xf); + g->ops.pmu.save_zbc(g, 0xf); } if (g->elpg_enabled) { diff --git a/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c index d32bd7d04..49e2e75ab 100644 --- a/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c @@ -308,7 +308,6 @@ static const struct gpu_ops vgpu_gp10b_ops = { .add_depth = NULL, .set_table = vgpu_gr_add_zbc, .query_table = vgpu_gr_query_zbc, - .pmu_save = NULL, .stencil_query_table = NULL, .load_stencil_default_tbl = NULL, .add_type_stencil = NULL, @@ -551,6 +550,7 @@ static const struct gpu_ops vgpu_gp10b_ops = { .dump_secure_fuses = NULL, .reset_engine = NULL, .is_engine_in_reset = NULL, + .save_zbc = NULL, }, .clk_arb = { .check_clk_arb_support = gp10b_check_clk_arb_support, diff --git a/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c index fa355813d..d51c155a9 100644 --- a/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c @@ -348,7 +348,6 @@ static const struct gpu_ops vgpu_gv11b_ops = { .add_depth = NULL, .set_table = vgpu_gr_add_zbc, .query_table = vgpu_gr_query_zbc, - .pmu_save = NULL, .stencil_query_table = gr_gv11b_zbc_s_query_table, .load_stencil_default_tbl = gr_gv11b_load_stencil_default_tbl, @@ -625,6 +624,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { .pmu_nsbootstrap = NULL, .pmu_pg_set_sub_feature_mask = NULL, .is_pmu_supported = NULL, + .save_zbc = NULL, }, .clk_arb = { .check_clk_arb_support = gp10b_check_clk_arb_support, diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 7f74d3e73..32dd063be 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c @@ -2562,41 +2562,6 @@ int gr_gk20a_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr, return 0; } -void gr_gk20a_pmu_save_zbc(struct gk20a *g, u32 entries) -{ - struct fifo_gk20a *f = &g->fifo; - struct fifo_engine_info_gk20a *gr_info = NULL; - int ret; - u32 engine_id; - - engine_id = nvgpu_engine_get_gr_eng_id(g); - gr_info = (f->engine_info + engine_id); - - ret = gk20a_fifo_disable_engine_activity(g, gr_info, true); - if (ret != 0) { - nvgpu_err(g, - "failed to disable gr engine activity"); - return; - } - - ret = g->ops.gr.wait_empty(g); - if (ret != 0) { - nvgpu_err(g, - "failed to idle graphics"); - goto clean_up; - } - - /* update zbc */ - g->ops.gr.zbc.pmu_save(g, entries); - -clean_up: - ret = gk20a_fifo_enable_engine_activity(g, gr_info); - if (ret != 0) { - nvgpu_err(g, - "failed to enable gr engine activity"); - } -} - int gr_gk20a_add_zbc(struct gk20a *g, struct gr_gk20a *gr, struct zbc_entry *zbc_val) { @@ -2702,7 +2667,7 @@ int gr_gk20a_add_zbc(struct gk20a *g, struct gr_gk20a *gr, /* update zbc for elpg only when new entry is added */ entries = max(gr->max_used_color_index, gr->max_used_depth_index); - g->ops.gr.zbc.pmu_save(g, entries); + g->ops.pmu.save_zbc(g, entries); } err_mutex: diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index 224ea1314..5c12f58e1 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h @@ -548,7 +548,6 @@ int gr_gk20a_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr, struct zbc_entry *color_val, u32 index); int gr_gk20a_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr, struct zbc_entry *depth_val, u32 index); -void gr_gk20a_pmu_save_zbc(struct gk20a *g, u32 entries); int gr_gk20a_wait_idle(struct gk20a *g); int gr_gk20a_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, bool *post_event, struct channel_gk20a *fault_ch, diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 96a1223ad..1b6137dde 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c @@ -415,7 +415,6 @@ static const struct gpu_ops gm20b_ops = { .add_depth = gr_gk20a_add_zbc_depth, .set_table = gk20a_gr_zbc_set_table, .query_table = gr_gk20a_query_zbc, - .pmu_save = gk20a_pmu_save_zbc, .stencil_query_table = NULL, .load_stencil_default_tbl = NULL, .add_type_stencil = NULL, @@ -674,6 +673,7 @@ static const struct gpu_ops gm20b_ops = { .is_engine_in_reset = gk20a_pmu_is_engine_in_reset, .get_irqdest = gk20a_pmu_get_irqdest, .is_debug_mode_enabled = gm20b_pmu_is_debug_mode_en, + .save_zbc = gk20a_pmu_save_zbc, }, .clk = { .init_clk_support = gm20b_init_clk_support, diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 600a291e5..719b0dc93 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -458,7 +458,6 @@ static const struct gpu_ops gp10b_ops = { .add_depth = gr_gp10b_add_zbc_depth, .set_table = gk20a_gr_zbc_set_table, .query_table = gr_gk20a_query_zbc, - .pmu_save = gk20a_pmu_save_zbc, .stencil_query_table = NULL, .load_stencil_default_tbl = NULL, .add_type_stencil = NULL, @@ -745,6 +744,7 @@ static const struct gpu_ops gp10b_ops = { .is_engine_in_reset = gk20a_pmu_is_engine_in_reset, .get_irqdest = gk20a_pmu_get_irqdest, .is_debug_mode_enabled = gm20b_pmu_is_debug_mode_en, + .save_zbc = gk20a_pmu_save_zbc, }, .clk_arb = { .check_clk_arb_support = gp10b_check_clk_arb_support, diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index f914d9fb0..d1afa19ae 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -584,7 +584,6 @@ static const struct gpu_ops gv100_ops = { .add_depth = gr_gp10b_add_zbc_depth, .set_table = gk20a_gr_zbc_set_table, .query_table = gr_gk20a_query_zbc, - .pmu_save = gk20a_pmu_save_zbc, .stencil_query_table = gr_gv11b_zbc_s_query_table, .load_stencil_default_tbl = gr_gv11b_load_stencil_default_tbl, @@ -927,6 +926,7 @@ static const struct gpu_ops gv100_ops = { .setup_apertures = gp106_pmu_setup_apertures, .secured_pmu_start = gm20b_secured_pmu_start, .create_ssmd_lookup_table = nvgpu_pmu_create_ssmd_lookup_table, + .save_zbc = gk20a_pmu_save_zbc, }, .clk = { .init_clk_support = gv100_init_clk_support, diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index a8da4e209..e8ca25a26 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -543,7 +543,6 @@ static const struct gpu_ops gv11b_ops = { .add_depth = gr_gp10b_add_zbc_depth, .set_table = gk20a_gr_zbc_set_table, .query_table = gr_gk20a_query_zbc, - .pmu_save = gk20a_pmu_save_zbc, .stencil_query_table = gr_gv11b_zbc_s_query_table, .load_stencil_default_tbl = gr_gv11b_load_stencil_default_tbl, @@ -873,6 +872,7 @@ static const struct gpu_ops gv11b_ops = { .get_irqdest = gv11b_pmu_get_irqdest, .handle_ext_irq = gv11b_pmu_handle_ext_irq, .is_debug_mode_enabled = gm20b_pmu_is_debug_mode_en, + .save_zbc = gk20a_pmu_save_zbc, }, .clk_arb = { .check_clk_arb_support = gp10b_check_clk_arb_support, diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index bdd09ada1..23b6d0fea 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -629,7 +629,6 @@ struct gpu_ops { struct gr_gk20a *gr); int (*add_stencil)(struct gk20a *g, struct gr_gk20a *gr, struct zbc_entry *s_val, u32 index); - void (*pmu_save)(struct gk20a *g, u32 entries); bool (*add_type_stencil)(struct gk20a *g, struct gr_gk20a *gr, struct zbc_entry *zbc_val, int *ret_val); @@ -1253,6 +1252,7 @@ struct gpu_ops { u64 err_cnt); } err_ops; void (*create_ssmd_lookup_table)(struct nvgpu_pmu *pmu); + void (*save_zbc)(struct gk20a *g, u32 entries); } pmu; struct { int (*init_debugfs)(struct gk20a *g); diff --git a/drivers/gpu/nvgpu/tu104/hal_tu104.c b/drivers/gpu/nvgpu/tu104/hal_tu104.c index 499c221c5..4394536d2 100644 --- a/drivers/gpu/nvgpu/tu104/hal_tu104.c +++ b/drivers/gpu/nvgpu/tu104/hal_tu104.c @@ -608,7 +608,6 @@ static const struct gpu_ops tu104_ops = { .add_depth = gr_gp10b_add_zbc_depth, .set_table = gk20a_gr_zbc_set_table, .query_table = gr_gk20a_query_zbc, - .pmu_save = gk20a_pmu_save_zbc, .stencil_query_table = gr_gv11b_zbc_s_query_table, .load_stencil_default_tbl = gr_gv11b_load_stencil_default_tbl, @@ -959,6 +958,7 @@ static const struct gpu_ops tu104_ops = { .setup_apertures = gp106_pmu_setup_apertures, .secured_pmu_start = gm20b_secured_pmu_start, .create_ssmd_lookup_table = nvgpu_pmu_create_ssmd_lookup_table, + .save_zbc = gk20a_pmu_save_zbc, }, .clk = { .init_clk_support = gv100_init_clk_support,