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gpu: nvgpu: add profiler apis to manage PMA stream

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Support new IOCTL to manage PMA stream meta data by adding below API
nvgpu_prof_ioctl_pma_stream_update_get_put()

Add nvgpu_perfbuf_update_get_put() to handle all the updates coming
from userspace and to pass all required information.

Add gops.perf.update_get_put() to handle all HW accesses required in
perf HW unit.

Add gops.perf.bind_mem_bytes_buffer_addr() to bind the available bytes
buffer while binding HWPM streamout.

Bug 2510974
Jira NVGPU-5360

Change-Id: Ibacc2299b845e47776babc081759dfc4afde34fe
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2406484
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Deepak Nibade
2020-08-06 11:34:34 +05:30
committed by Alex Waterman
parent 5844151a93
commit 221475f753
11 changed files with 159 additions and 0 deletions
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37
drivers/gpu/nvgpu/hal/perf/perf_gv11b.c
View File

@@ -88,6 +88,43 @@ void gv11b_perf_disable_membuf(struct gk20a *g)
nvgpu_writel(g, perf_pmasys_outsize_r(), 0);
}
void gv11b_perf_bind_mem_bytes_buffer_addr(struct gk20a *g, u64 buf_addr)
{
u32 addr_lo;
buf_addr = buf_addr >> perf_pmasys_mem_bytes_addr_ptr_b();
addr_lo = nvgpu_safe_cast_u64_to_u32(buf_addr);
nvgpu_writel(g, perf_pmasys_mem_bytes_addr_r(),
perf_pmasys_mem_bytes_addr_ptr_f(addr_lo));
}
int gv11b_perf_update_get_put(struct gk20a *g, u64 bytes_consumed,
bool update_available_bytes, u64 *put_ptr,
bool *overflowed)
{
u32 val;
nvgpu_writel(g, perf_pmasys_mem_bump_r(), bytes_consumed);
if (update_available_bytes) {
val = nvgpu_readl(g, perf_pmasys_control_r());
val = set_field(val, perf_pmasys_control_update_bytes_m(),
perf_pmasys_control_update_bytes_doit_f());
nvgpu_writel(g, perf_pmasys_control_r(), val);
}
if (put_ptr) {
*put_ptr = (u64)nvgpu_readl(g, perf_pmasys_mem_head_r());
}
if (overflowed) {
*overflowed = g->ops.perf.get_membuf_overflow_status(g);
}
return 0;
}
void gv11b_perf_init_inst_block(struct gk20a *g, struct nvgpu_mem *inst_block)
{
u32 inst_block_ptr = nvgpu_inst_block_ptr(g, inst_block);

5
drivers/gpu/nvgpu/hal/perf/perf_gv11b.h
View File

@@ -40,6 +40,11 @@ void gv11b_perf_membuf_reset_streaming(struct gk20a *g);
void gv11b_perf_enable_membuf(struct gk20a *g, u32 size, u64 buf_addr);
void gv11b_perf_disable_membuf(struct gk20a *g);
void gv11b_perf_bind_mem_bytes_buffer_addr(struct gk20a *g, u64 buf_addr);
int gv11b_perf_update_get_put(struct gk20a *g, u64 bytes_consumed, bool update_available_bytes,
u64 *put_ptr, bool *overflowed);
void gv11b_perf_init_inst_block(struct gk20a *g, struct nvgpu_mem *inst_block);
void gv11b_perf_deinit_inst_block(struct gk20a *g);