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gpu: nvgpu: add description for tpc id and slice id checks

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This patch adds description to emphasize the necessity to do the
maximum value check for TPC and SLICE IDs.

JIRA NVGPU-3867

Change-Id: I69029bb3b3888590b5a1d1869058e9ae125775bb
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2183875
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Rajesh Devaraj
2019-08-27 01:13:39 +05:30
committed by mobile promotions
parent d5d31e5b17
commit 2272e04861
2 changed files with 40 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

42
drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b_fusa.c
View File

@@ -900,7 +900,11 @@ void gv11b_gr_intr_set_hww_esr_report_mask(struct gk20a *g)
static void gv11b_gr_intr_report_l1_tag_uncorrected_err(struct gk20a *g,
u32 l1_tag_ecc_status, u32 gpc, u32 tpc)
{
if (tpc > 255U) {
/* This check has been added to ensure that the TPC id is less than
* 8-bits and hence, it can be packed as part of LSB 8-bits along with
* the GPC id while reporting SM related ECC errors.
*/
if (tpc > U8_MAX) {
nvgpu_log(g, gpu_dbg_intr, "Invalid tpc id=%d", tpc);
tpc = tpc & 0xFFU;
}
@@ -931,7 +935,11 @@ static void gv11b_gr_intr_report_l1_tag_uncorrected_err(struct gk20a *g,
static void gv11b_gr_intr_report_l1_tag_corrected_err(struct gk20a *g,
u32 l1_tag_ecc_status, u32 gpc, u32 tpc)
{
if (tpc > 255U) {
/* This check has been added to ensure that the TPC id is less than
* 8-bits and hence, it can be packed as part of LSB 8-bits along with
* the GPC id while reporting SM related ECC errors.
*/
if (tpc > U8_MAX) {
nvgpu_log(g, gpu_dbg_intr, "Invalid tpc id=%d", tpc);
tpc = tpc & 0xFFU;
}
@@ -1114,7 +1122,11 @@ static void gv11b_gr_intr_handle_lrf_exception(struct gk20a *g, u32 gpc, u32 tpc
is_lrf_ecc_uncorrected_total_err_overflow =
gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_total_counter_overflow_v(lrf_ecc_status) != 0U;
if (tpc > 255U) {
/* This check has been added to ensure that the TPC id is less than
* 8-bits and hence, it can be packed as part of LSB 8-bits along with
* the GPC id while reporting SM related ECC errors.
*/
if (tpc > U8_MAX) {
nvgpu_log(g, gpu_dbg_intr, "Invalid tpc id=%d", tpc);
tpc = tpc & 0xFFU;
}
@@ -1221,7 +1233,11 @@ static void gv11b_gr_intr_handle_cbu_exception(struct gk20a *g, u32 gpc, u32 tpc
is_cbu_ecc_uncorrected_total_err_overflow =
gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_total_counter_overflow_v(cbu_ecc_status) != 0U;
if (tpc > 255U) {
/* This check has been added to ensure that the TPC id is less than
* 8-bits and hence, it can be packed as part of LSB 8-bits along with
* the GPC id while reporting SM related ECC errors.
*/
if (tpc > U8_MAX) {
nvgpu_log(g, gpu_dbg_intr, "Invalid tpc id=%d", tpc);
tpc = tpc & 0xFFU;
}
@@ -1322,7 +1338,11 @@ static void gv11b_gr_intr_handle_l1_data_exception(struct gk20a *g, u32 gpc, u32
is_l1_data_ecc_uncorrected_total_err_overflow =
gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_total_counter_overflow_v(l1_data_ecc_status) != 0U;
if (tpc > 255U) {
/* This check has been added to ensure that the TPC id is less than
* 8-bits and hence, it can be packed as part of LSB 8-bits along with
* the GPC id while reporting SM related ECC errors.
*/
if (tpc > U8_MAX) {
nvgpu_log(g, gpu_dbg_intr, "Invalid tpc id=%d", tpc);
tpc = tpc & 0xFFU;
}
@@ -1381,7 +1401,11 @@ static void gv11b_gr_intr_handle_l1_data_exception(struct gk20a *g, u32 gpc, u32
static void gv11b_gr_intr_report_icache_uncorrected_err(struct gk20a *g,
u32 icache_ecc_status, u32 gpc, u32 tpc)
{
if (tpc > 255U) {
/* This check has been added to ensure that the TPC id is less than
* 8-bits and hence, it can be packed as part of LSB 8-bits along with
* the GPC id while reporting SM related ECC errors.
*/
if (tpc > U8_MAX) {
nvgpu_log(g, gpu_dbg_intr, "Invalid tpc id=%d", tpc);
tpc = tpc & 0xFFU;
}
@@ -1418,7 +1442,11 @@ static void gv11b_gr_intr_report_icache_uncorrected_err(struct gk20a *g,
static void gv11b_gr_intr_report_icache_corrected_err(struct gk20a *g,
u32 icache_ecc_status, u32 gpc, u32 tpc)
{
if (tpc > 255U) {
/* This check has been added to ensure that the TPC id is less than
* 8-bits and hence, it can be packed as part of LSB 8-bits along with
* the GPC id while reporting SM related ECC errors.
*/
if (tpc > U8_MAX) {
nvgpu_log(g, gpu_dbg_intr, "Invalid tpc id=%d", tpc);
tpc = tpc & 0xFFU;
}

6
drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_gv11b_fusa.c
View File

@@ -166,7 +166,11 @@ static void gv11b_ltc_intr_handle_lts_interrupts(struct gk20a *g,
"ltc:%d lts: %d cache ecc interrupt intr: 0x%x",
ltc, slice, ltc_intr3);
if (slice > 255U) {
/* This check has been added to ensure that the slice id is less
* than 8-bits and hence, it can be packed as part of LSB 8-bits
* along with the LTC id while reporting LTC related ECC errors.
*/
if (slice > U8_MAX) {
nvgpu_log(g, gpu_dbg_intr, "Invalid slice id=%d",
slice);
slice = slice & 0xFFU;