Revert "gpu: nvgpu: change stall intr handling order"

This reverts commit 35f0cf0efe as
it caused lp0 suspend/resume failure.

Bug 1886110

Change-Id: Ib62207650344180361b6529f716f77b84528cd56
Signed-off-by: Rajkumar Kasirajan <rkasirajan@nvidia.com>
Reviewed-on: http://git-master/r/1317986
(cherry picked from commit e4a131a98d)
Reviewed-on: http://git-master/r/1320905
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/gk20a/mc_gk20a.c

@@ -1,7 +1,7 @@
 /*
  * GK20A Master Control
  *
- * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2016, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -121,12 +121,6 @@ irqreturn_t mc_gk20a_intr_thread_stall(struct gk20a *g)
 
 	gk20a_dbg(gpu_dbg_intr, "stall intr %08x\n", mc_intr_0);
 
-	/* handle critical interrupts first */
-	if (mc_intr_0 & mc_intr_0_pbus_pending_f())
-		gk20a_pbus_isr(g);
-	if (mc_intr_0 & mc_intr_0_priv_ring_pending_f())
-		gk20a_priv_ring_isr(g);
-
 	for (engine_id_idx = 0; engine_id_idx < g->fifo.num_engines; engine_id_idx++) {
 		active_engine_id = g->fifo.active_engines_list[engine_id_idx];
 
@@ -151,8 +145,12 @@ irqreturn_t mc_gk20a_intr_thread_stall(struct gk20a *g)
 		gk20a_fifo_isr(g);
 	if (mc_intr_0 & mc_intr_0_pmu_pending_f())
 		gk20a_pmu_isr(g);
+	if (mc_intr_0 & mc_intr_0_priv_ring_pending_f())
+		gk20a_priv_ring_isr(g);
 	if (mc_intr_0 & mc_intr_0_ltc_pending_f())
 		g->ops.ltc.isr(g);
+	if (mc_intr_0 & mc_intr_0_pbus_pending_f())
+		gk20a_pbus_isr(g);
 
 	/* sync handled irq counter before re-enabling interrupts */
 	atomic_set(&g->sw_irq_stall_last_handled, hw_irq_count);

drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c

@@ -76,6 +76,8 @@ void gk20a_priv_ring_isr(struct gk20a *g)
 	u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
 	struct gk20a_platform *platform = dev_get_drvdata(g->dev);
 
+	if (platform->is_fmodel)
+		return;
 
 	status0 = gk20a_readl(g, pri_ringmaster_intr_status0_r());
 	status1 = gk20a_readl(g, pri_ringmaster_intr_status1_r());
@@ -88,6 +90,7 @@ void gk20a_priv_ring_isr(struct gk20a *g)
 	    pri_ringmaster_intr_status0_overflow_fault_v(status0) != 0) {
 		gk20a_reset_priv_ring(g);
 	}
+
 	if (pri_ringmaster_intr_status0_gbl_write_error_sys_v(status0) != 0) {
 		gk20a_dbg(gpu_dbg_intr, "SYS write error. ADR %08x WRDAT %08x INFO %08x, CODE %08x",
 			gk20a_readl(g, pri_ringstation_sys_priv_error_adr_r()),
@@ -106,9 +109,6 @@ void gk20a_priv_ring_isr(struct gk20a *g)
 		}
 	}
 
-	if (platform->is_fmodel)
-		return;
-
 	cmd = gk20a_readl(g, pri_ringmaster_command_r());
 	cmd = set_field(cmd, pri_ringmaster_command_cmd_m(),
 		pri_ringmaster_command_cmd_ack_interrupt_f());

drivers/gpu/nvgpu/gp10b/mc_gp10b.c

@@ -1,7 +1,7 @@
 /*
  * GP20B master
  *
- * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2016, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -133,12 +133,6 @@ irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g)
 
 	gk20a_dbg(gpu_dbg_intr, "stall intr %08x\n", mc_intr_0);
 
-	/* handle critical interrupts first */
-	if (mc_intr_0 & mc_intr_pbus_pending_f())
-		gk20a_pbus_isr(g);
-	if (mc_intr_0 & mc_intr_priv_ring_pending_f())
-		gk20a_priv_ring_isr(g);
-
 	for (engine_id_idx = 0; engine_id_idx < g->fifo.num_engines; engine_id_idx++) {
 		active_engine_id = g->fifo.active_engines_list[engine_id_idx];
 
@@ -163,8 +157,12 @@ irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g)
 		gk20a_fifo_isr(g);
 	if (mc_intr_0 & mc_intr_pmu_pending_f())
 		gk20a_pmu_isr(g);
+	if (mc_intr_0 & mc_intr_priv_ring_pending_f())
+		gk20a_priv_ring_isr(g);
 	if (mc_intr_0 & mc_intr_ltc_pending_f())
 		g->ops.ltc.isr(g);
+	if (mc_intr_0 & mc_intr_pbus_pending_f())
+		gk20a_pbus_isr(g);
 
 	/* sync handled irq counter before re-enabling interrupts */
 	atomic_set(&g->sw_irq_stall_last_handled, hw_irq_count);