From 22c3ce37a75ab1234ed5180682ee3631164bd58c Mon Sep 17 00:00:00 2001 From: Divya Singhatwaria Date: Tue, 23 Mar 2021 18:34:12 +0530 Subject: [PATCH] gpu: nvgpu: ga10b: add fuse_ctrl register Add the following registers: fuse_ctrl_opt_gpc_r() fuse_ctrl_opt_fbp_r() These registers are needed to add floorsweeping support for GPC and FBP JIRA NVGPU-6433 Change-Id: I795e0812bd9abb69cdf552b8ccb460f026a06803 Signed-off-by: Divya Singhatwaria Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2559485 Reviewed-by: svcacv Reviewed-by: Mahantesh Kumbar Reviewed-by: svc_kernel_abi Reviewed-by: Vijayakumar Subbu Reviewed-by: mobile promotions Tested-by: mobile promotions GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_fuse_ga10b.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_fuse_ga10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_fuse_ga10b.h index 7e5d4a5fe..7e4897386 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_fuse_ga10b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_fuse_ga10b.h @@ -66,6 +66,8 @@ (nvgpu_safe_add_u32(0x00820838U, nvgpu_safe_mult_u32((i), 4U))) #define fuse_ctrl_opt_ltc_fbp_r(i)\ (nvgpu_safe_add_u32(0x00820970U, nvgpu_safe_mult_u32((i), 4U))) +#define fuse_ctrl_opt_gpc_r() (0x0082081cU) +#define fuse_ctrl_opt_fbp_r() (0x00820938U) #define fuse_status_opt_fbio_r() (0x00820c14U) #define fuse_status_opt_fbp_r() (0x00820d38U) #define fuse_opt_ecc_en_r() (0x00820228U)