From 22cb47c077d6c70d66f148c1ba70cc364bf079a4 Mon Sep 17 00:00:00 2001 From: Vinod G Date: Mon, 25 Mar 2019 18:08:50 -0700 Subject: [PATCH] gpu: nvgpu: move fbp_en_mask hal to hal.gr.init Move fbp_en_mask hal to hal.gr.init. Calls to g->ops.gr.fbp_en_mask is modified to g->ops.gr.init.fbp_en_mask JIRA NVGPU-2951 Change-Id: I555ec3691226a9dd8555fa91f5ec90010d83ddd3 Signed-off-by: Vinod G Reviewed-on: https://git-master.nvidia.com/r/2081370 Reviewed-by: mobile promotions Tested-by: mobile promotions --- .../nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c | 2 +- .../nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c | 2 +- drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 2 +- drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 22 +------------------ drivers/gpu/nvgpu/gm20b/gr_gm20b.h | 1 - drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 2 +- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 2 +- drivers/gpu/nvgpu/gv100/hal_gv100.c | 2 +- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 2 +- drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.c | 21 ++++++++++++++++++ drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.h | 1 + drivers/gpu/nvgpu/include/nvgpu/gk20a.h | 2 +- drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c | 2 +- drivers/gpu/nvgpu/tu104/hal_tu104.c | 2 +- 14 files changed, 33 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c index 94ce875e9..d176c4256 100644 --- a/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c @@ -143,7 +143,6 @@ static const struct gpu_ops vgpu_gp10b_ops = { gr_gp10b_update_ctxsw_preemption_mode, .dump_gr_regs = NULL, .update_pc_sampling = vgpu_gr_update_pc_sampling, - .get_fbp_en_mask = vgpu_gr_get_fbp_en_mask, .get_rop_l2_en_mask = vgpu_gr_rop_l2_en_mask, .init_sm_dsm_reg_info = gr_gm20b_init_sm_dsm_reg_info, .init_cyclestats = vgpu_gr_init_cyclestats, @@ -318,6 +317,7 @@ static const struct gpu_ops vgpu_gp10b_ops = { }, #endif /* CONFIG_GK20A_CTXSW_TRACE */ .init = { + .get_fbp_en_mask = vgpu_gr_get_fbp_en_mask, .fs_state = vgpu_gr_init_fs_state, .get_bundle_cb_default_size = gm20b_gr_init_get_bundle_cb_default_size, diff --git a/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c index 626a1bed6..4e7be3fbf 100644 --- a/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c @@ -164,7 +164,6 @@ static const struct gpu_ops vgpu_gv11b_ops = { gr_gv11b_update_ctxsw_preemption_mode, .dump_gr_regs = NULL, .update_pc_sampling = vgpu_gr_update_pc_sampling, - .get_fbp_en_mask = vgpu_gr_get_fbp_en_mask, .get_rop_l2_en_mask = vgpu_gr_rop_l2_en_mask, .init_sm_dsm_reg_info = gv11b_gr_init_sm_dsm_reg_info, .init_cyclestats = vgpu_gr_init_cyclestats, @@ -369,6 +368,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { }, #endif /* CONFIG_GK20A_CTXSW_TRACE */ .init = { + .get_fbp_en_mask = vgpu_gr_get_fbp_en_mask, .fs_state = vgpu_gr_init_fs_state, .get_bundle_cb_default_size = gv11b_gr_init_get_bundle_cb_default_size, diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 246921824..bf94fdd9b 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c @@ -1770,7 +1770,7 @@ static int gr_gk20a_init_gr_config(struct gk20a *g, struct gr_gk20a *gr) gr->num_fbps = g->ops.priv_ring.get_fbp_count(g); gr->max_fbps_count = g->ops.top.get_max_fbps_count(g); - gr->fbp_en_mask = g->ops.gr.get_fbp_en_mask(g); + gr->fbp_en_mask = g->ops.gr.init.get_fbp_en_mask(g); if (gr->fbp_rop_l2_en_mask == NULL) { gr->fbp_rop_l2_en_mask = diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index e87526a70..805533057 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c @@ -718,26 +718,6 @@ int gr_gm20b_update_pc_sampling(struct channel_gk20a *c, return 0; } -u32 gr_gm20b_get_fbp_en_mask(struct gk20a *g) -{ - u32 fbp_en_mask; - u32 max_fbps_count; - - max_fbps_count = g->ops.top.get_max_fbps_count(g); - - /* - * Read active fbp mask from fuse - * Note that 0:enable and 1:disable in value read from fuse so we've to - * flip the bits. - * Also set unused bits to zero - */ - fbp_en_mask = g->ops.fuse.fuse_status_opt_fbp(g); - fbp_en_mask = ~fbp_en_mask; - fbp_en_mask = fbp_en_mask & (BIT32(max_fbps_count) - 1U); - - return fbp_en_mask; -} - u32 *gr_gm20b_rop_l2_en_mask(struct gk20a *g) { struct gr_gk20a *gr = &g->gr; @@ -749,7 +729,7 @@ u32 *gr_gm20b_rop_l2_en_mask(struct gk20a *g) max_fbps_count = g->ops.top.get_max_fbps_count(g); max_ltc_per_fbp = g->ops.top.get_max_ltc_per_fbp(g); rop_l2_all_en = BIT32(max_ltc_per_fbp) - 1U; - fbp_en_mask = gr_gm20b_get_fbp_en_mask(g); + fbp_en_mask = g->ops.gr.init.get_fbp_en_mask(g); /* mask of Rop_L2 for each FBP */ for_each_set_bit(i, &fbp_en_mask, max_fbps_count) { diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h index d4d548c87..01df78158 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h @@ -79,7 +79,6 @@ int gr_gm20b_dump_gr_status_regs(struct gk20a *g, struct gk20a_debug_output *o); int gr_gm20b_update_pc_sampling(struct channel_gk20a *c, bool enable); -u32 gr_gm20b_get_fbp_en_mask(struct gk20a *g); u32 *gr_gm20b_rop_l2_en_mask(struct gk20a *g); void gr_gm20b_init_cyclestats(struct gk20a *g); void gr_gm20b_bpt_reg_info(struct gk20a *g, struct nvgpu_warpstate *w_state); diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 4d5a8bf4a..4e3c9557c 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c @@ -268,7 +268,6 @@ static const struct gpu_ops gm20b_ops = { gr_gm20b_update_ctxsw_preemption_mode, .dump_gr_regs = gr_gm20b_dump_gr_status_regs, .update_pc_sampling = gr_gm20b_update_pc_sampling, - .get_fbp_en_mask = gr_gm20b_get_fbp_en_mask, .get_rop_l2_en_mask = gr_gm20b_rop_l2_en_mask, .init_sm_dsm_reg_info = gr_gm20b_init_sm_dsm_reg_info, .init_cyclestats = gr_gm20b_init_cyclestats, @@ -412,6 +411,7 @@ static const struct gpu_ops gm20b_ops = { .program_zcull_mapping = gm20b_gr_program_zcull_mapping, }, .init = { + .get_fbp_en_mask = gm20b_gr_init_get_fbp_en_mask, .lg_coalesce = gm20b_gr_init_lg_coalesce, .su_coalesce = gm20b_gr_init_su_coalesce, .pes_vsc_stream = gm20b_gr_init_pes_vsc_stream, diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 05d780280..87435c9c5 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -293,7 +293,6 @@ static const struct gpu_ops gp10b_ops = { gr_gp10b_update_ctxsw_preemption_mode, .dump_gr_regs = gr_gp10b_dump_gr_status_regs, .update_pc_sampling = gr_gm20b_update_pc_sampling, - .get_fbp_en_mask = gr_gm20b_get_fbp_en_mask, .get_rop_l2_en_mask = gr_gm20b_rop_l2_en_mask, .init_sm_dsm_reg_info = gr_gm20b_init_sm_dsm_reg_info, .init_cyclestats = gr_gm20b_init_cyclestats, @@ -485,6 +484,7 @@ static const struct gpu_ops gp10b_ops = { .program_zcull_mapping = gm20b_gr_program_zcull_mapping, }, .init = { + .get_fbp_en_mask = gm20b_gr_init_get_fbp_en_mask, .lg_coalesce = gm20b_gr_init_lg_coalesce, .su_coalesce = gm20b_gr_init_su_coalesce, .pes_vsc_stream = gm20b_gr_init_pes_vsc_stream, diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 84f6ced6b..374c4fa32 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -405,7 +405,6 @@ static const struct gpu_ops gv100_ops = { gr_gp10b_update_ctxsw_preemption_mode, .dump_gr_regs = gr_gv11b_dump_gr_status_regs, .update_pc_sampling = gr_gm20b_update_pc_sampling, - .get_fbp_en_mask = gr_gm20b_get_fbp_en_mask, .get_rop_l2_en_mask = gr_gm20b_rop_l2_en_mask, .init_sm_dsm_reg_info = gv11b_gr_init_sm_dsm_reg_info, .init_cyclestats = gr_gm20b_init_cyclestats, @@ -629,6 +628,7 @@ static const struct gpu_ops gv100_ops = { gv100_gr_hwpm_map_get_active_fbpa_mask, }, .init = { + .get_fbp_en_mask = gm20b_gr_init_get_fbp_en_mask, .lg_coalesce = gm20b_gr_init_lg_coalesce, .su_coalesce = gm20b_gr_init_su_coalesce, .pes_vsc_stream = gm20b_gr_init_pes_vsc_stream, diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 607e26e36..453420493 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -357,7 +357,6 @@ static const struct gpu_ops gv11b_ops = { gr_gv11b_update_ctxsw_preemption_mode, .dump_gr_regs = gr_gv11b_dump_gr_status_regs, .update_pc_sampling = gr_gm20b_update_pc_sampling, - .get_fbp_en_mask = gr_gm20b_get_fbp_en_mask, .get_rop_l2_en_mask = gr_gm20b_rop_l2_en_mask, .init_sm_dsm_reg_info = gv11b_gr_init_sm_dsm_reg_info, .init_cyclestats = gr_gm20b_init_cyclestats, @@ -588,6 +587,7 @@ static const struct gpu_ops gv11b_ops = { gv100_gr_hwpm_map_align_regs_perf_pma, }, .init = { + .get_fbp_en_mask = gm20b_gr_init_get_fbp_en_mask, .lg_coalesce = gm20b_gr_init_lg_coalesce, .su_coalesce = gm20b_gr_init_su_coalesce, .pes_vsc_stream = gm20b_gr_init_pes_vsc_stream, diff --git a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.c b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.c index 5e5bf2f01..90ce0fd2f 100644 --- a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.c +++ b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.c @@ -43,6 +43,26 @@ #define FE_PWR_MODE_TIMEOUT_DEFAULT_US 10U #define FECS_CTXSW_RESET_DELAY_US 10U +u32 gm20b_gr_init_get_fbp_en_mask(struct gk20a *g) +{ + u32 fbp_en_mask; + u32 max_fbps_count; + + max_fbps_count = g->ops.top.get_max_fbps_count(g); + + /* + * Read active fbp mask from fuse + * Note that 0:enable and 1:disable in value read from fuse so we've to + * flip the bits. + * Also set unused bits to zero + */ + fbp_en_mask = g->ops.fuse.fuse_status_opt_fbp(g); + fbp_en_mask = ~fbp_en_mask; + fbp_en_mask = fbp_en_mask & (BIT32(max_fbps_count) - 1U); + + return fbp_en_mask; +} + void gm20b_gr_init_lg_coalesce(struct gk20a *g, u32 data) { u32 val; @@ -71,6 +91,7 @@ void gm20b_gr_init_su_coalesce(struct gk20a *g, u32 data) void gm20b_gr_init_pes_vsc_stream(struct gk20a *g) { u32 data = nvgpu_readl(g, gr_gpc0_ppc0_pes_vsc_strem_r()); + data = set_field(data, gr_gpc0_ppc0_pes_vsc_strem_master_pe_m(), gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f()); nvgpu_writel(g, gr_gpc0_ppc0_pes_vsc_strem_r(), data); diff --git a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.h b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.h index 7f0a63409..74d9a13fa 100644 --- a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.h +++ b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.h @@ -31,6 +31,7 @@ struct nvgpu_gr_config; struct netlist_av_list; struct nvgpu_gr_config; +u32 gm20b_gr_init_get_fbp_en_mask(struct gk20a *g); void gm20b_gr_init_lg_coalesce(struct gk20a *g, u32 data); void gm20b_gr_init_su_coalesce(struct gk20a *g, u32 data); void gm20b_gr_init_pes_vsc_stream(struct gk20a *g); diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index 7aca8add4..502b8540c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -335,7 +335,6 @@ struct gpu_ops { struct gk20a_debug_output *o); int (*update_pc_sampling)(struct channel_gk20a *ch, bool enable); - u32 (*get_fbp_en_mask)(struct gk20a *g); u32* (*get_rop_l2_en_mask)(struct gk20a *g); void (*init_sm_dsm_reg_info)(void); void (*init_ovr_sm_dsm_perf)(void); @@ -661,6 +660,7 @@ struct gpu_ops { } hwpm_map; struct { + u32 (*get_fbp_en_mask)(struct gk20a *g); void (*lg_coalesce)(struct gk20a *g, u32 data); void (*su_coalesce)(struct gk20a *g, u32 data); void (*pes_vsc_stream)(struct gk20a *g); diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c b/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c index 8a458179f..ca41e790e 100644 --- a/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c +++ b/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c @@ -338,7 +338,7 @@ gk20a_ctrl_ioctl_gpu_characteristics( strlcpy(gpu.chipname, g->name, sizeof(gpu.chipname)); gpu.max_fbps_count = g->ops.top.get_max_fbps_count(g); - gpu.fbp_en_mask = g->ops.gr.get_fbp_en_mask(g); + gpu.fbp_en_mask = g->ops.gr.init.get_fbp_en_mask(g); gpu.max_ltc_per_fbp = g->ops.top.get_max_ltc_per_fbp(g); gpu.max_lts_per_ltc = g->ops.top.get_max_lts_per_ltc(g); gpu.gr_compbit_store_base_hw = g->cbc->compbit_store.base_hw; diff --git a/drivers/gpu/nvgpu/tu104/hal_tu104.c b/drivers/gpu/nvgpu/tu104/hal_tu104.c index 880303952..79622a9d9 100644 --- a/drivers/gpu/nvgpu/tu104/hal_tu104.c +++ b/drivers/gpu/nvgpu/tu104/hal_tu104.c @@ -426,7 +426,6 @@ static const struct gpu_ops tu104_ops = { gr_gv11b_update_ctxsw_preemption_mode, .dump_gr_regs = gr_gv11b_dump_gr_status_regs, .update_pc_sampling = gr_gm20b_update_pc_sampling, - .get_fbp_en_mask = gr_gm20b_get_fbp_en_mask, .get_rop_l2_en_mask = gr_gm20b_rop_l2_en_mask, .init_sm_dsm_reg_info = gr_tu104_init_sm_dsm_reg_info, .init_cyclestats = gr_gm20b_init_cyclestats, @@ -658,6 +657,7 @@ static const struct gpu_ops tu104_ops = { gv100_gr_hwpm_map_get_active_fbpa_mask, }, .init = { + .get_fbp_en_mask = gm20b_gr_init_get_fbp_en_mask, .lg_coalesce = gm20b_gr_init_lg_coalesce, .su_coalesce = gm20b_gr_init_su_coalesce, .pes_vsc_stream = gm20b_gr_init_pes_vsc_stream,