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gpu: nvgpu: vgpu: add read ptimer support

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Bug 1395833

Change-Id: Id0d427b6a1ddaecfeec33c61a6161679cf596c92
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1159588
(cherry picked from commit d33aa89420990626fb377c56ed5517a00f717c2a)
Reviewed-on: http://git-master/r/1158897
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
Richard Zhao
2016-06-08 14:57:41 -07:00
committed by Terje Bergstrom
parent 86225cb04e
commit 22d0233d3a
2 changed files with 30 additions and 0 deletions
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24
drivers/gpu/nvgpu/vgpu/vgpu.c
View File

@@ -312,6 +312,29 @@ static int vgpu_init_gpu_characteristics(struct gk20a *g)
return 0; return 0;
} }
static int vgpu_read_ptimer(struct gk20a *g, u64 *value)
{
struct gk20a_platform *platform = gk20a_get_platform(g->dev);
struct tegra_vgpu_cmd_msg msg = {0};
struct tegra_vgpu_read_ptimer_params *p = &msg.params.read_ptimer;
int err;
gk20a_dbg_fn("");
msg.cmd = TEGRA_VGPU_CMD_READ_PTIMER;
msg.handle = platform->virt_handle;
err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
err = err ? err : msg.ret;
if (!err)
*value = p->time;
else
gk20a_err(dev_from_gk20a(g),
"vgpu read ptimer failed, err=%d", err);
return err;
}
void vgpu_init_hal_common(struct gk20a *g) void vgpu_init_hal_common(struct gk20a *g)
{ {
struct gpu_ops *gops = &g->ops; struct gpu_ops *gops = &g->ops;
@@ -324,6 +347,7 @@ void vgpu_init_hal_common(struct gk20a *g)
vgpu_init_fecs_trace_ops(gops); vgpu_init_fecs_trace_ops(gops);
vgpu_init_tsg_ops(gops); vgpu_init_tsg_ops(gops);
gops->chip_init_gpu_characteristics = vgpu_init_gpu_characteristics; gops->chip_init_gpu_characteristics = vgpu_init_gpu_characteristics;
gops->read_ptimer = vgpu_read_ptimer;
} }
static int vgpu_init_hal(struct gk20a *g) static int vgpu_init_hal(struct gk20a *g)

6
include/linux/tegra_vgpu.h
View File

@@ -95,6 +95,7 @@ enum {
TEGRA_VGPU_CMD_TSG_SET_RUNLIST_INTERLEAVE, TEGRA_VGPU_CMD_TSG_SET_RUNLIST_INTERLEAVE,
TEGRA_VGPU_CMD_CHANNEL_FORCE_RESET, TEGRA_VGPU_CMD_CHANNEL_FORCE_RESET,
TEGRA_VGPU_CMD_CHANNEL_ENABLE, TEGRA_VGPU_CMD_CHANNEL_ENABLE,
TEGRA_VGPU_CMD_READ_PTIMER,
}; };
struct tegra_vgpu_connect_params { struct tegra_vgpu_connect_params {
@@ -389,6 +390,10 @@ struct tegra_vgpu_tsg_runlist_interleave_params {
u32 level; u32 level;
}; };
struct tegra_vgpu_read_ptimer_params {
u64 time;
};
struct tegra_vgpu_cmd_msg { struct tegra_vgpu_cmd_msg {
u32 cmd; u32 cmd;
int ret; int ret;
@@ -429,6 +434,7 @@ struct tegra_vgpu_cmd_msg {
struct tegra_vgpu_tsg_preempt_params tsg_preempt; struct tegra_vgpu_tsg_preempt_params tsg_preempt;
struct tegra_vgpu_tsg_timeslice_params tsg_timeslice; struct tegra_vgpu_tsg_timeslice_params tsg_timeslice;
struct tegra_vgpu_tsg_runlist_interleave_params tsg_interleave; struct tegra_vgpu_tsg_runlist_interleave_params tsg_interleave;
struct tegra_vgpu_read_ptimer_params read_ptimer;
char padding[192]; char padding[192];
} params; } params;
}; };