diff --git a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b.h b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b.h
index 272d1f9c9..7492c12d3 100644
--- a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b.h
+++ b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b.h
@@ -65,7 +65,6 @@ void gv11b_gr_intr_set_shader_cut_collector(struct gk20a *g, u32 data);
 void gv11b_gr_intr_set_skedcheck(struct gk20a *g, u32 data);
 int gv11b_gr_intr_handle_sw_method(struct gk20a *g, u32 addr,
 				     u32 class_num, u32 offset, u32 data);
-void gv11b_gr_intr_set_shader_exceptions(struct gk20a *g, u32 data);
 void gv11b_gr_intr_handle_gcc_exception(struct gk20a *g, u32 gpc,
 			u32 gpc_exception,
 			u32 *corrected_err, u32 *uncorrected_err);
@@ -110,6 +109,10 @@ u64 gv11b_gr_intr_get_sm_hww_warp_esr_pc(struct gk20a *g, u32 offset);
 
 u32 gv11b_gr_intr_ctxsw_checksum_mismatch_mailbox_val(void);
 
+#ifdef CONFIG_NVGPU_HAL_NON_FUSA
+void gv11b_gr_intr_set_shader_exceptions(struct gk20a *g, u32 data);
+#endif
+
 #if defined(CONFIG_NVGPU_DEBUGGER) && defined(CONFIG_NVGPU_GRAPHICS)
 void gv11b_gr_intr_set_tex_in_dbg(struct gk20a *g, u32 data);
 #endif
diff --git a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b_fusa.c b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b_fusa.c
index 8cc2be63f..9cff116d7 100644
--- a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b_fusa.c
+++ b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b_fusa.c
@@ -155,9 +155,11 @@ int gv11b_gr_intr_handle_sw_method(struct gk20a *g, u32 addr,
 
 	if (class_num == VOLTA_COMPUTE_A) {
 		switch (offset << 2) {
+#ifdef CONFIG_NVGPU_HAL_NON_FUSA
 		case NVC0C0_SET_SHADER_EXCEPTIONS:
 			g->ops.gr.intr.set_shader_exceptions(g, data);
 			break;
+#endif
 		case NVC3C0_SET_SKEDCHECK:
 			gv11b_gr_intr_set_skedcheck(g, data);
 			break;
@@ -218,20 +220,6 @@ fail:
 	return ret;
 }
 
-void gv11b_gr_intr_set_shader_exceptions(struct gk20a *g, u32 data)
-{
-	nvgpu_log_fn(g, " ");
-
-	if (data == NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE) {
-		nvgpu_writel(g, gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r(),
-				 0);
-		nvgpu_writel(g, gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r(),
-				 0);
-	} else {
-		g->ops.gr.intr.set_hww_esr_report_mask(g);
-	}
-}
-
 void gv11b_gr_intr_handle_gcc_exception(struct gk20a *g, u32 gpc,
 				u32 gpc_exception,
 				u32 *corrected_err, u32 *uncorrected_err)
@@ -1747,6 +1735,22 @@ u32 gv11b_gr_intr_ctxsw_checksum_mismatch_mailbox_val(void)
 	return gr_fecs_ctxsw_mailbox_value_ctxsw_checksum_mismatch_v();
 }
 
+#ifdef CONFIG_NVGPU_HAL_NON_FUSA
+void gv11b_gr_intr_set_shader_exceptions(struct gk20a *g, u32 data)
+{
+	nvgpu_log_fn(g, " ");
+
+	if (data == NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE) {
+		nvgpu_writel(g, gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r(),
+				 0);
+		nvgpu_writel(g, gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r(),
+				 0);
+	} else {
+		g->ops.gr.intr.set_hww_esr_report_mask(g);
+	}
+}
+#endif
+
 #if defined(CONFIG_NVGPU_DEBUGGER) && defined(CONFIG_NVGPU_GRAPHICS)
 void gv11b_gr_intr_set_tex_in_dbg(struct gk20a *g, u32 data)
 {
diff --git a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c
index 7987ef7bf..0aa925185 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c
@@ -628,8 +628,6 @@ static const struct gpu_ops gv11b_ops = {
 		.intr = {
 			.handle_fecs_error = gv11b_gr_intr_handle_fecs_error,
 			.handle_sw_method = gv11b_gr_intr_handle_sw_method,
-			.set_shader_exceptions =
-					gv11b_gr_intr_set_shader_exceptions,
 			.handle_class_error =
 					gm20b_gr_intr_handle_class_error,
 			.clear_pending_interrupts =
@@ -701,6 +699,8 @@ static const struct gpu_ops gv11b_ops = {
 			.get_ctxsw_checksum_mismatch_mailbox_val =
 				gv11b_gr_intr_ctxsw_checksum_mismatch_mailbox_val,
 #ifdef CONFIG_NVGPU_HAL_NON_FUSA
+			.set_shader_exceptions =
+					gv11b_gr_intr_set_shader_exceptions,
 			.tpc_exception_sm_enable =
 				gm20b_gr_intr_tpc_exception_sm_enable,
 #endif