diff --git a/drivers/gpu/nvgpu/hal/fifo/pbdma_gm20b.h b/drivers/gpu/nvgpu/hal/fifo/pbdma_gm20b.h index 71355ef6c..0a99a7c4a 100644 --- a/drivers/gpu/nvgpu/hal/fifo/pbdma_gm20b.h +++ b/drivers/gpu/nvgpu/hal/fifo/pbdma_gm20b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -30,6 +30,7 @@ struct nvgpu_debug_context; struct nvgpu_channel_dump_info; struct nvgpu_gpfifo_entry; struct nvgpu_pbdma_status_info; +struct nvgpu_device; bool gm20b_pbdma_handle_intr_0(struct gk20a *g, u32 pbdma_id, u32 pbdma_intr_0, u32 *error_notifier); @@ -55,7 +56,7 @@ u32 gm20b_pbdma_get_gp_base(u64 gpfifo_base); u32 gm20b_pbdma_get_gp_base_hi(u64 gpfifo_base, u32 gpfifo_entry); u32 gm20b_pbdma_get_fc_subdevice(void); -u32 gm20b_pbdma_get_fc_target(void); +u32 gm20b_pbdma_get_fc_target(const struct nvgpu_device *dev); u32 gm20b_pbdma_get_ctrl_hce_priv_mode_yes(void); u32 gm20b_pbdma_get_userd_aperture_mask(struct gk20a *g, struct nvgpu_mem *mem); u32 gm20b_pbdma_get_userd_addr(u32 addr_lo); diff --git a/drivers/gpu/nvgpu/hal/fifo/pbdma_gm20b_fusa.c b/drivers/gpu/nvgpu/hal/fifo/pbdma_gm20b_fusa.c index 03ff70f6e..d24cdf918 100644 --- a/drivers/gpu/nvgpu/hal/fifo/pbdma_gm20b_fusa.c +++ b/drivers/gpu/nvgpu/hal/fifo/pbdma_gm20b_fusa.c @@ -35,6 +35,7 @@ #include #include #include +#include #include @@ -385,7 +386,7 @@ u32 gm20b_pbdma_get_fc_subdevice(void) pbdma_subdevice_channel_dma_enable_f()); } -u32 gm20b_pbdma_get_fc_target(void) +u32 gm20b_pbdma_get_fc_target(const struct nvgpu_device *dev) { return pbdma_target_engine_sw_f(); } diff --git a/drivers/gpu/nvgpu/hal/fifo/pbdma_gv11b.h b/drivers/gpu/nvgpu/hal/fifo/pbdma_gv11b.h index 5c15191be..8b3a98362 100644 --- a/drivers/gpu/nvgpu/hal/fifo/pbdma_gv11b.h +++ b/drivers/gpu/nvgpu/hal/fifo/pbdma_gv11b.h @@ -26,6 +26,7 @@ #include struct gk20a; +struct nvgpu_device; void gv11b_pbdma_setup_hw(struct gk20a *g); void gv11b_pbdma_intr_enable(struct gk20a *g, bool enable); @@ -35,7 +36,7 @@ bool gv11b_pbdma_handle_intr_1(struct gk20a *g, u32 pbdma_id, u32 pbdma_intr_1, u32 *error_notifier); u32 gv11b_pbdma_channel_fatal_0_intr_descs(void); u32 gv11b_pbdma_get_fc_pb_header(void); -u32 gv11b_pbdma_get_fc_target(void); +u32 gv11b_pbdma_get_fc_target(const struct nvgpu_device *dev); u32 gv11b_pbdma_set_channel_info_veid(u32 subctx_id); u32 gv11b_pbdma_config_userd_writeback_enable(u32 v); diff --git a/drivers/gpu/nvgpu/hal/fifo/pbdma_gv11b_fusa.c b/drivers/gpu/nvgpu/hal/fifo/pbdma_gv11b_fusa.c index df3d9329d..476e78284 100644 --- a/drivers/gpu/nvgpu/hal/fifo/pbdma_gv11b_fusa.c +++ b/drivers/gpu/nvgpu/hal/fifo/pbdma_gv11b_fusa.c @@ -26,6 +26,7 @@ #include #include #include +#include #include @@ -263,9 +264,9 @@ u32 gv11b_pbdma_get_fc_pb_header(void) pbdma_pb_header_type_inc_f()); } -u32 gv11b_pbdma_get_fc_target(void) +u32 gv11b_pbdma_get_fc_target(const struct nvgpu_device *dev) { - return (gm20b_pbdma_get_fc_target() | + return (gm20b_pbdma_get_fc_target(dev) | pbdma_target_eng_ctx_valid_true_f() | pbdma_target_ce_ctx_valid_true_f()); } diff --git a/drivers/gpu/nvgpu/hal/fifo/ramfc_gk20a.c b/drivers/gpu/nvgpu/hal/fifo/ramfc_gk20a.c index 179b4c280..9e515ac34 100644 --- a/drivers/gpu/nvgpu/hal/fifo/ramfc_gk20a.c +++ b/drivers/gpu/nvgpu/hal/fifo/ramfc_gk20a.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2011-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -86,7 +86,7 @@ int gk20a_ramfc_setup(struct nvgpu_channel *ch, u64 gpfifo_base, g->ops.pbdma.get_fc_subdevice()); nvgpu_mem_wr32(g, mem, ram_fc_target_w(), - g->ops.pbdma.get_fc_target()); + g->ops.pbdma.get_fc_target(NULL)); nvgpu_mem_wr32(g, mem, ram_fc_acquire_w(), g->ops.pbdma.acquire_val(pbdma_acquire_timeout)); diff --git a/drivers/gpu/nvgpu/hal/fifo/ramfc_gp10b.c b/drivers/gpu/nvgpu/hal/fifo/ramfc_gp10b.c index a731cea79..711e8358d 100644 --- a/drivers/gpu/nvgpu/hal/fifo/ramfc_gp10b.c +++ b/drivers/gpu/nvgpu/hal/fifo/ramfc_gp10b.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -62,7 +62,7 @@ int gp10b_ramfc_setup(struct nvgpu_channel *ch, u64 gpfifo_base, g->ops.pbdma.get_fc_subdevice()); nvgpu_mem_wr32(g, mem, ram_fc_target_w(), - g->ops.pbdma.get_fc_target()); + g->ops.pbdma.get_fc_target(NULL)); nvgpu_mem_wr32(g, mem, ram_fc_acquire_w(), g->ops.pbdma.acquire_val(pbdma_acquire_timeout)); diff --git a/drivers/gpu/nvgpu/hal/fifo/ramfc_gv11b_fusa.c b/drivers/gpu/nvgpu/hal/fifo/ramfc_gv11b_fusa.c index dcc83fbbc..9521a6a03 100644 --- a/drivers/gpu/nvgpu/hal/fifo/ramfc_gv11b_fusa.c +++ b/drivers/gpu/nvgpu/hal/fifo/ramfc_gv11b_fusa.c @@ -72,7 +72,7 @@ int gv11b_ramfc_setup(struct nvgpu_channel *ch, u64 gpfifo_base, g->ops.pbdma.get_fc_subdevice()); nvgpu_mem_wr32(g, mem, ram_fc_target_w(), - g->ops.pbdma.get_fc_target()); + g->ops.pbdma.get_fc_target(NULL)); nvgpu_mem_wr32(g, mem, ram_fc_acquire_w(), g->ops.pbdma.acquire_val(pbdma_acquire_timeout)); diff --git a/drivers/gpu/nvgpu/hal/fifo/ramfc_tu104.c b/drivers/gpu/nvgpu/hal/fifo/ramfc_tu104.c index ab5ab13ba..7bceadf4f 100644 --- a/drivers/gpu/nvgpu/hal/fifo/ramfc_tu104.c +++ b/drivers/gpu/nvgpu/hal/fifo/ramfc_tu104.c @@ -60,7 +60,7 @@ int tu104_ramfc_setup(struct nvgpu_channel *ch, u64 gpfifo_base, g->ops.pbdma.get_fc_subdevice()); nvgpu_mem_wr32(g, mem, ram_fc_target_w(), - g->ops.pbdma.get_fc_target()); + g->ops.pbdma.get_fc_target(NULL)); nvgpu_mem_wr32(g, mem, ram_fc_acquire_w(), g->ops.pbdma.acquire_val(pbdma_acquire_timeout)); diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/pbdma.h b/drivers/gpu/nvgpu/include/nvgpu/gops/pbdma.h index aa7d9964c..e0c3d3ce5 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops/pbdma.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/pbdma.h @@ -27,6 +27,7 @@ struct gk20a; struct nvgpu_gpfifo_entry; struct nvgpu_pbdma_status_info; +struct nvgpu_device; /** @cond DOXYGEN_SHOULD_SKIP_THIS */ @@ -68,7 +69,7 @@ struct gops_pbdma { u32 (*get_fc_formats)(void); u32 (*get_fc_pb_header)(void); u32 (*get_fc_subdevice)(void); - u32 (*get_fc_target)(void); + u32 (*get_fc_target)(const struct nvgpu_device *dev); u32 (*get_ctrl_hce_priv_mode_yes)(void); u32 (*get_userd_aperture_mask)(struct gk20a *g, struct nvgpu_mem *mem); diff --git a/userspace/units/fifo/pbdma/gv11b/nvgpu-pbdma-gv11b.c b/userspace/units/fifo/pbdma/gv11b/nvgpu-pbdma-gv11b.c index 8c0607849..4963b32b9 100644 --- a/userspace/units/fifo/pbdma/gv11b/nvgpu-pbdma-gv11b.c +++ b/userspace/units/fifo/pbdma/gv11b/nvgpu-pbdma-gv11b.c @@ -338,7 +338,7 @@ int test_gv11b_pbdma_get_fc(struct unit_module *m, pbdma_pb_header_first_true_f() | pbdma_pb_header_type_inc_f()), goto done); - unit_assert(gv11b_pbdma_get_fc_target() == + unit_assert(gv11b_pbdma_get_fc_target(NULL) == (pbdma_target_engine_sw_f() | pbdma_target_eng_ctx_valid_true_f() | pbdma_target_ce_ctx_valid_true_f()), goto done); diff --git a/userspace/units/fifo/ramfc/gv11b/nvgpu-ramfc-gv11b.c b/userspace/units/fifo/ramfc/gv11b/nvgpu-ramfc-gv11b.c index 34c3511d3..bae3ab33d 100644 --- a/userspace/units/fifo/ramfc/gv11b/nvgpu-ramfc-gv11b.c +++ b/userspace/units/fifo/ramfc/gv11b/nvgpu-ramfc-gv11b.c @@ -89,7 +89,7 @@ static u32 stub_pbdma_get_fc_subdevice(void) return 0U; } -static u32 stub_pbdma_get_fc_target(void) +static u32 stub_pbdma_get_fc_target(const struct nvgpu_device *dev) { global_count++; return 0U;