diff --git a/Makefile.umbrella.tmk b/Makefile.umbrella.tmk index 1f563dcae..405e22fb3 100644 --- a/Makefile.umbrella.tmk +++ b/Makefile.umbrella.tmk @@ -80,6 +80,7 @@ NV_REPOSITORY_COMPONENTS += userspace/units/fifo/engine/gp10b NV_REPOSITORY_COMPONENTS += userspace/units/fifo/engine/gv100 NV_REPOSITORY_COMPONENTS += userspace/units/fifo/engine/gv11b NV_REPOSITORY_COMPONENTS += userspace/units/fifo/fifo/gk20a +NV_REPOSITORY_COMPONENTS += userspace/units/fifo/fifo/gv11b NV_REPOSITORY_COMPONENTS += userspace/units/fifo/pbdma NV_REPOSITORY_COMPONENTS += userspace/units/fifo/pbdma/gv11b NV_REPOSITORY_COMPONENTS += userspace/units/fifo/pbdma/gm20b diff --git a/drivers/gpu/nvgpu/libnvgpu-drv_safe.export b/drivers/gpu/nvgpu/libnvgpu-drv_safe.export index 8fd50d2b0..4aeed7620 100644 --- a/drivers/gpu/nvgpu/libnvgpu-drv_safe.export +++ b/drivers/gpu/nvgpu/libnvgpu-drv_safe.export @@ -104,8 +104,16 @@ gv11b_fb_init_hw gv11b_fb_is_fault_buf_enabled gv11b_fb_intr_disable gv11b_fb_intr_is_mmu_fault_pending +gv11b_fifo_handle_sched_error +gv11b_fifo_intr_0_enable +gv11b_fifo_intr_0_isr +gv11b_fifo_intr_set_recover_mask +gv11b_fifo_intr_unset_recover_mask +gv11b_fifo_mmu_fault_id_to_pbdma_id gv11b_get_litter_value gv11b_gpu_phys_addr +gv11b_init_fifo_reset_enable_hw +gv11b_init_fifo_setup_hw gv11b_init_hal gv11b_is_fault_engine_subid_gpc gv11b_mm_is_bar1_supported diff --git a/drivers/gpu/nvgpu/os/posix/os_posix.h b/drivers/gpu/nvgpu/os/posix/os_posix.h index 313016289..03ce9522a 100644 --- a/drivers/gpu/nvgpu/os/posix/os_posix.h +++ b/drivers/gpu/nvgpu/os/posix/os_posix.h @@ -59,6 +59,7 @@ struct nvgpu_os_posix { * Parameters to change SOC behavior */ bool is_soc_t194_a01; + bool is_silicon; }; static inline struct nvgpu_os_posix *nvgpu_os_posix_from_gk20a(struct gk20a *g) diff --git a/drivers/gpu/nvgpu/os/posix/soc.c b/drivers/gpu/nvgpu/os/posix/soc.c index 17e2e7160..10fd95abb 100644 --- a/drivers/gpu/nvgpu/os/posix/soc.c +++ b/drivers/gpu/nvgpu/os/posix/soc.c @@ -26,7 +26,9 @@ bool nvgpu_platform_is_silicon(struct gk20a *g) { - return false; + struct nvgpu_os_posix *p = nvgpu_os_posix_from_gk20a(g); + + return p->is_silicon; } bool nvgpu_platform_is_simulation(struct gk20a *g) diff --git a/userspace/Makefile.sources b/userspace/Makefile.sources index 7c785065f..dc6d26189 100644 --- a/userspace/Makefile.sources +++ b/userspace/Makefile.sources @@ -79,6 +79,7 @@ UNITS := \ $(UNIT_SRC)/fbp \ $(UNIT_SRC)/fifo \ $(UNIT_SRC)/fifo/fifo/gk20a \ + $(UNIT_SRC)/fifo/fifo/gv11b \ $(UNIT_SRC)/fifo/channel \ $(UNIT_SRC)/fifo/channel/gk20a \ $(UNIT_SRC)/fifo/channel/gm20b \ diff --git a/userspace/SWUTS.h b/userspace/SWUTS.h index d59579a9b..05bc19c2c 100644 --- a/userspace/SWUTS.h +++ b/userspace/SWUTS.h @@ -47,6 +47,7 @@ * - @ref SWUTS-fifo-engine-gv100 * - @ref SWUTS-fifo-engine-gv11b * - @ref SWUTS-fifo-fifo-gk20a + * - @ref SWUTS-fifo-fifo-gv11b * - @ref SWUTS-fifo-pbdma * - @ref SWUTS-fifo-pbdma-gm20b * - @ref SWUTS-fifo-pbdma-gp10b diff --git a/userspace/SWUTS.sources b/userspace/SWUTS.sources index 716ea943a..3437b9d95 100644 --- a/userspace/SWUTS.sources +++ b/userspace/SWUTS.sources @@ -18,6 +18,8 @@ INPUT += ../../../userspace/units/fifo/engine/gv100/nvgpu-engine-gv100.h INPUT += ../../../userspace/units/fifo/engine/gv11b/nvgpu-engine-gv11b.h INPUT += ../../../userspace/units/fifo/fifo/gk20a/nvgpu-fifo-gk20a.h INPUT += ../../../userspace/units/fifo/fifo/gk20a/nvgpu-fifo-intr-gk20a.h +INPUT += ../../../userspace/units/fifo/fifo/gv11b/nvgpu-fifo-gv11b.h +INPUT += ../../../userspace/units/fifo/fifo/gv11b/nvgpu-fifo-intr-gv11b.h INPUT += ../../../userspace/units/fifo/pbdma/nvgpu-pbdma.h INPUT += ../../../userspace/units/fifo/pbdma/gm20b/nvgpu-pbdma-gm20b.h INPUT += ../../../userspace/units/fifo/pbdma/gp10b/nvgpu-pbdma-gp10b.h diff --git a/userspace/required_tests.json b/userspace/required_tests.json index 2edff6819..9f5739bf4 100644 --- a/userspace/required_tests.json +++ b/userspace/required_tests.json @@ -1619,6 +1619,54 @@ "unit": "nvgpu_fifo_gk20a", "test_level": 0 }, + { + "test": "test_gv11b_fifo_handle_sched_error", + "case": "handle_sched_error", + "unit": "nvgpu_fifo_gv11b", + "test_level": 0 + }, + { + "test": "test_gv11b_fifo_init_hw", + "case": "init_hw", + "unit": "nvgpu_fifo_gv11b", + "test_level": 0 + }, + { + "test": "test_fifo_init_support", + "case": "init_support", + "unit": "nvgpu_fifo_gv11b", + "test_level": 0 + }, + { + "test": "test_gv11b_fifo_intr_0_enable", + "case": "intr_0_enable", + "unit": "nvgpu_fifo_gv11b", + "test_level": 0 + }, + { + "test": "test_gv11b_fifo_intr_0_isr", + "case": "intr_0_isr", + "unit": "nvgpu_fifo_gv11b", + "test_level": 0 + }, + { + "test": "test_gv11b_fifo_intr_recover_mask", + "case": "intr_recover_mask", + "unit": "nvgpu_fifo_gv11b", + "test_level": 0 + }, + { + "test": "test_gv11b_fifo_mmu_fault_id_to_pbdma_id", + "case": "mmu_fault_id_to_pbdma_id", + "unit": "nvgpu_fifo_gv11b", + "test_level": 0 + }, + { + "test": "test_fifo_remove_support", + "case": "remove_support", + "unit": "nvgpu_fifo_gv11b", + "test_level": 0 + }, { "test": "test_gr_config_count", "case": "config_check_init", diff --git a/userspace/units/fifo/fifo/gv11b/Makefile b/userspace/units/fifo/fifo/gv11b/Makefile new file mode 100644 index 000000000..8fd4286d0 --- /dev/null +++ b/userspace/units/fifo/fifo/gv11b/Makefile @@ -0,0 +1,32 @@ +# Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. + +.SUFFIXES: + +OBJS = nvgpu-fifo-gv11b.o nvgpu-fifo-intr-gv11b.o +MODULE = nvgpu-fifo-gv11b + +LIB_PATHS += -lnvgpu-fifo +include ../../../Makefile.units + +lib$(MODULE).so: fifo + +fifo: + $(MAKE) -C ../.. diff --git a/userspace/units/fifo/fifo/gv11b/Makefile.interface.tmk b/userspace/units/fifo/fifo/gv11b/Makefile.interface.tmk new file mode 100644 index 000000000..a9de29c4e --- /dev/null +++ b/userspace/units/fifo/fifo/gv11b/Makefile.interface.tmk @@ -0,0 +1,35 @@ +################################### tell Emacs this is a -*- makefile-gmake -*- +# +# Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. +# +# tmake for SW Mobile component makefile +# +############################################################################### + +NVGPU_UNIT_NAME=nvgpu-fifo-gv11b + +include $(NV_SOURCE)/kernel/nvgpu/userspace/units/Makefile.units.common.interface.tmk + +# Local Variables: +# indent-tabs-mode: t +# tab-width: 8 +# End: +# vi: set tabstop=8 noexpandtab: diff --git a/userspace/units/fifo/fifo/gv11b/Makefile.tmk b/userspace/units/fifo/fifo/gv11b/Makefile.tmk new file mode 100644 index 000000000..8f1e7067b --- /dev/null +++ b/userspace/units/fifo/fifo/gv11b/Makefile.tmk @@ -0,0 +1,40 @@ +################################### tell Emacs this is a -*- makefile-gmake -*- +# +# Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. +# +# tmake for SW Mobile component makefile +# +############################################################################### + +NVGPU_UNIT_NAME = nvgpu-fifo-gv11b +NVGPU_UNIT_SRCS = nvgpu-fifo-gv11b.c nvgpu-fifo-intr-gv11b.c + +NVGPU_UNIT_INTERFACE_DIRS := \ + $(NV_SOURCE)/kernel/nvgpu/userspace/units/fifo \ + $(NV_SOURCE)/kernel/nvgpu/drivers/gpu/nvgpu + +include $(NV_SOURCE)/kernel/nvgpu/userspace/units/Makefile.units.common.tmk + +# Local Variables: +# indent-tabs-mode: t +# tab-width: 8 +# End: +# vi: set tabstop=8 noexpandtab: diff --git a/userspace/units/fifo/fifo/gv11b/nvgpu-fifo-gv11b.c b/userspace/units/fifo/fifo/gv11b/nvgpu-fifo-gv11b.c new file mode 100644 index 000000000..dce2e7828 --- /dev/null +++ b/userspace/units/fifo/fifo/gv11b/nvgpu-fifo-gv11b.c @@ -0,0 +1,142 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "hal/fifo/fifo_gv11b.h" +#include + +#include "../../nvgpu-fifo.h" +#include "nvgpu-fifo-gv11b.h" +#include "nvgpu-fifo-intr-gv11b.h" + +#ifdef FIFO_GV11B_UNIT_DEBUG +#undef unit_verbose +#define unit_verbose unit_info +#else +#define unit_verbose(unit, msg, ...) \ + do { \ + if (0) { \ + unit_info(unit, msg, ##__VA_ARGS__); \ + } \ + } while (0) +#endif + +#define assert(cond) unit_assert(cond, goto done) + +int test_gv11b_fifo_init_hw(struct unit_module *m, + struct gk20a *g, void *args) +{ + int ret = UNIT_FAIL; + struct nvgpu_os_posix *p = nvgpu_os_posix_from_gk20a(g); + int i; + + for (i = 0; i < 2; i++) { + p->is_silicon = (i > 0); + + if (!nvgpu_platform_is_silicon(g)) { + nvgpu_writel(g, fifo_fb_timeout_r(), 0); + g->ptimer_src_freq = 32500000; + } + + gv11b_init_fifo_reset_enable_hw(g); + + if (!nvgpu_platform_is_silicon(g)) { + assert(nvgpu_readl(g, fifo_fb_timeout_r()) != 0); + } + + nvgpu_writel(g, fifo_userd_writeback_r(), 0); + gv11b_init_fifo_setup_hw(g); + assert(nvgpu_readl(g, fifo_userd_writeback_r()) != 0); + } + + ret = UNIT_SUCCESS; +done: + return ret; +} + +#define INVALID_ID 0xffffffffU + +int test_gv11b_fifo_mmu_fault_id_to_pbdma_id(struct unit_module *m, + struct gk20a *g, void *args) +{ + int ret = UNIT_FAIL; + u32 reg_val; + u32 num_pbdma = 3; + u32 fault_id_pbdma0 = 15; + u32 pbdma_id; + u32 fault_id; + u32 i; + + reg_val = (fault_id_pbdma0 << 16) | num_pbdma; + nvgpu_writel(g, fifo_cfg0_r(), reg_val); + + pbdma_id = gv11b_fifo_mmu_fault_id_to_pbdma_id(g, 1); + assert(pbdma_id == INVALID_ID); + + pbdma_id = gv11b_fifo_mmu_fault_id_to_pbdma_id(g, fault_id_pbdma0 + num_pbdma); + assert(pbdma_id == INVALID_ID); + + for (i = 0; i < num_pbdma; i++) { + fault_id = fault_id_pbdma0 + i; + pbdma_id = gv11b_fifo_mmu_fault_id_to_pbdma_id(g, fault_id); + assert(pbdma_id == i); + } + + ret = UNIT_SUCCESS; +done: + return ret; +} + +struct unit_module_test nvgpu_fifo_gv11b_tests[] = { + UNIT_TEST(init_support, test_fifo_init_support, NULL, 0), + + /* fifo gv11b */ + UNIT_TEST(init_hw, test_gv11b_fifo_init_hw, NULL, 0), + UNIT_TEST(mmu_fault_id_to_pbdma_id, test_gv11b_fifo_mmu_fault_id_to_pbdma_id, NULL, 0), + + /* fifo intr gv11b */ + UNIT_TEST(intr_0_enable, test_gv11b_fifo_intr_0_enable, NULL, 0), + UNIT_TEST(handle_sched_error, test_gv11b_fifo_handle_sched_error, NULL, 0), + UNIT_TEST(intr_0_isr, test_gv11b_fifo_intr_0_isr, NULL, 0), + UNIT_TEST(intr_recover_mask, test_gv11b_fifo_intr_recover_mask, NULL, 0), + + UNIT_TEST(remove_support, test_fifo_remove_support, NULL, 0), +}; + +UNIT_MODULE(nvgpu_fifo_gv11b, nvgpu_fifo_gv11b_tests, UNIT_PRIO_NVGPU_TEST); diff --git a/userspace/units/fifo/fifo/gv11b/nvgpu-fifo-gv11b.h b/userspace/units/fifo/fifo/gv11b/nvgpu-fifo-gv11b.h new file mode 100644 index 000000000..c68d39046 --- /dev/null +++ b/userspace/units/fifo/fifo/gv11b/nvgpu-fifo-gv11b.h @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef UNIT_NVGPU_FIFO_GV11B_H +#define UNIT_NVGPU_FIFO_GV11B_H + +#include + +struct unit_module; +struct gk20a; + +/** @addtogroup SWUTS-fifo-fifo-gv11b + * @{ + * + * Software Unit Test Specification for fifo/fifo/gv11b + */ + +/** + * Test specification for: test_gv11b_fifo_init_hw + * + * Description: Reset and enable HW + * + * Test Type: Feature based + * + * Targets: gv11b_init_fifo_reset_enable_hw, gv11b_init_fifo_setup_hw + * + * Input: test_fifo_init_support() run for this GPU + * + * Steps: + * - Check silicon platform case. + * - Call gv11b_init_fifo_reset_enable_hw and gv11b_init_fifo_setup_hw. + * - Check that userd writeback has been enabled. + * - Check path for non-silicon platform + * - Check that fifof fb timeout has been programmed. + * + * Output: Returns PASS if all branches gave expected results. FAIL otherwise. + */ +int test_gv11b_fifo_init_hw(struct unit_module *m, + struct gk20a *g, void *args); + +/** + * Test specification for: test_gv11b_fifo_mmu_fault_id_to_pbdma_id + * + * Description: Get PBDMA id from MMU fault + * + * Test Type: Feature based + * + * Targets: gv11b_fifo_mmu_fault_id_to_pbdma_id + * + * Input: test_fifo_init_support() run for this GPU + * + * Steps: + * - Set fifo_cfg0_r with 3 PBDMAs, starting at MMU fault_id 15. + * - Check that gv11b_fifo_mmu_fault_id_to_pbdma_id returns correct pbdma_id + * for all MMU fault_id in 15 <= mmu_fault_id < (15 + num_pbdma - 1) + * - Check that gv11b_fifo_mmu_fault_id_to_pbdma_id returns INVALID_ID when + * mmu_fault_id < 15 or mmu_fault_id >= (15 + num_pbdma). + * + * Output: Returns PASS if all branches gave expected results. FAIL otherwise. + */ +int test_gv11b_fifo_mmu_fault_id_to_pbdma_id(struct unit_module *m, + struct gk20a *g, void *args); + +/** + * @} + */ + +#endif /* UNIT_NVGPU_FIFO_GV11B_H */ diff --git a/userspace/units/fifo/fifo/gv11b/nvgpu-fifo-intr-gv11b.c b/userspace/units/fifo/fifo/gv11b/nvgpu-fifo-intr-gv11b.c new file mode 100644 index 000000000..27ff1ba88 --- /dev/null +++ b/userspace/units/fifo/fifo/gv11b/nvgpu-fifo-intr-gv11b.c @@ -0,0 +1,280 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "hal/fifo/fifo_gv11b.h" +#include "hal/fifo/fifo_intr_gv11b.h" + +#include + +#include "../../nvgpu-fifo.h" +#include "nvgpu-fifo-intr-gv11b.h" + +#define FIFO_GV11B_INTR_UNIT_DEBUG +#ifdef FIFO_GV11B_INTR_UNIT_DEBUG +#undef unit_verbose +#define unit_verbose unit_info +#else +#define unit_verbose(unit, msg, ...) \ + do { \ + if (0) { \ + unit_info(unit, msg, ##__VA_ARGS__); \ + } \ + } while (0) +#endif + +#define assert(cond) unit_assert(cond, goto done) +#define branches_str test_fifo_flags_str + +struct unit_ctx { + bool fifo_ctxsw_timeout_enable; + bool pbdma_intr_enable; +}; + +static struct unit_ctx u; + +static void stub_fifo_ctxsw_timeout_enable(struct gk20a *g, bool enable) +{ + u.fifo_ctxsw_timeout_enable = enable; +} + +static void stub_pbdma_intr_enable(struct gk20a *g, bool enable) +{ + u.pbdma_intr_enable = enable; +} + +int test_gv11b_fifo_intr_0_enable(struct unit_module *m, + struct gk20a *g, void *args) +{ + int ret = UNIT_FAIL; + struct gpu_ops gops = g->ops; + + g->ops.fifo.ctxsw_timeout_enable = stub_fifo_ctxsw_timeout_enable; + g->ops.pbdma.intr_enable = stub_pbdma_intr_enable; + + gv11b_fifo_intr_0_enable(g, true); + assert(u.fifo_ctxsw_timeout_enable); + assert(u.pbdma_intr_enable); + assert(nvgpu_readl(g, fifo_intr_runlist_r()) == U32_MAX); + assert(nvgpu_readl(g, fifo_intr_0_r()) == U32_MAX); + assert(nvgpu_readl(g, fifo_intr_en_0_r()) != 0); + + gv11b_fifo_intr_0_enable(g, false); + assert(!u.fifo_ctxsw_timeout_enable); + assert(!u.pbdma_intr_enable); + assert(nvgpu_readl(g, fifo_intr_en_0_r()) == 0); + + ret = UNIT_SUCCESS; +done: + g->ops = gops; + return ret; +} + +#define SCHED_ERROR_CODE_RL_REQ_TIMEOUT 0x0000000c + +int test_gv11b_fifo_handle_sched_error(struct unit_module *m, + struct gk20a *g, void *args) +{ + int ret = UNIT_FAIL; + + /* valid sched error code */ + nvgpu_writel(g, fifo_intr_sched_error_r(), SCHED_ERROR_CODE_RL_REQ_TIMEOUT); + gv11b_fifo_handle_sched_error(g); + + /* invalid sched error code */ + nvgpu_writel(g, fifo_intr_sched_error_r(), U32_MAX); + gv11b_fifo_handle_sched_error(g); + + /* valid sched error code + "recovery" */ + nvgpu_writel(g, fifo_intr_sched_error_r(), SCHED_ERROR_CODE_BAD_TSG); + gv11b_fifo_handle_sched_error(g); + + assert(ret != UNIT_SUCCESS); + ret = UNIT_SUCCESS; +done: + return ret; +} + +#define FIFO_NUM_INTRS_0 9 + + +static void writel_access_reg_fn(struct gk20a *g, + struct nvgpu_reg_access *access) +{ + u32 value = access->value; + + if (access->addr == fifo_intr_0_r() || + access->addr == fifo_intr_ctxsw_timeout_r()) { + /* write clears interrupts */ + value = nvgpu_posix_io_readl_reg_space(g, access->addr) & + ~access->value; + } + + nvgpu_posix_io_writel_reg_space(g, access->addr, value); +} + +static void readl_access_reg_fn(struct gk20a *g, + struct nvgpu_reg_access *access) +{ + access->value = nvgpu_posix_io_readl_reg_space(g, access->addr); +} + +#define FIFO_INTR_0_ERR_MASK \ + (fifo_intr_0_bind_error_pending_f() | \ + fifo_intr_0_sched_error_pending_f() | \ + fifo_intr_0_chsw_error_pending_f() | \ + fifo_intr_0_memop_timeout_pending_f() | \ + fifo_intr_0_lb_error_pending_f()) + +int test_gv11b_fifo_intr_0_isr(struct unit_module *m, + struct gk20a *g, void *args) +{ + int ret = UNIT_FAIL; + struct nvgpu_fifo *f = &g->fifo; + u32 branches = 0; + u32 fifo_intrs[FIFO_NUM_INTRS_0] = { + 2, /* not handled */ + fifo_intr_0_bind_error_pending_f(), + fifo_intr_0_chsw_error_pending_f(), + fifo_intr_0_memop_timeout_pending_f(), + fifo_intr_0_lb_error_pending_f(), + fifo_intr_0_runlist_event_pending_f(), + fifo_intr_0_pbdma_intr_pending_f(), + fifo_intr_0_sched_error_pending_f(), + fifo_intr_0_ctxsw_timeout_pending_f(), + }; + const char *labels[] = { + "invalid", + "bind_err", + "chsw_err", + "memop_timeout", + "lb_err", + "runlist_event", + "pbdma_intr", + "sched_err", + "ctxsw_timeout", + }; + u32 fifo_intr_0; + u32 val; + int i; + u32 intr_0_handled_mask = 0; + struct nvgpu_posix_io_callbacks *old_io; + struct nvgpu_posix_io_callbacks new_io = { + .readl = readl_access_reg_fn, + .writel = writel_access_reg_fn + }; + + old_io = nvgpu_posix_register_io(g, &new_io); + + for (i = 1; i < FIFO_NUM_INTRS_0; i++) { + intr_0_handled_mask |= fifo_intrs[i]; + } + + nvgpu_posix_io_writel_reg_space(g, fifo_intr_sched_error_r(), + SCHED_ERROR_CODE_RL_REQ_TIMEOUT); + + assert(f->sw_ready); + for (branches = 0; branches < BIT(FIFO_NUM_INTRS_0); branches++) { + + unit_verbose(m, "%s branches=%s\n", __func__, + branches_str(branches, labels)); + + fifo_intr_0 = 0; + for (i = 0; i < FIFO_NUM_INTRS_0; i++) { + if (branches & BIT(i)) { + fifo_intr_0 |= fifo_intrs[i]; + } + } + nvgpu_posix_io_writel_reg_space(g, fifo_intr_0_r(), + fifo_intr_0); + gv11b_fifo_intr_0_isr(g); + val = nvgpu_posix_io_readl_reg_space(g, fifo_intr_0_r()); + assert((val & intr_0_handled_mask) == 0); + assert((val & ~intr_0_handled_mask) == + (fifo_intr_0 & ~intr_0_handled_mask)); + } + + f->sw_ready = false; + nvgpu_posix_io_writel_reg_space(g, fifo_intr_0_r(), 0xcafe); + gv11b_fifo_intr_0_isr(g); + assert(nvgpu_posix_io_readl_reg_space(g, fifo_intr_0_r()) == 0); + f->sw_ready = true; + + ret = UNIT_SUCCESS; +done: + (void) nvgpu_posix_register_io(g, old_io); + return ret; +} + +int test_gv11b_fifo_intr_recover_mask(struct unit_module *m, + struct gk20a *g, void *args) +{ + int ret = UNIT_FAIL; + u32 intr_en_0; + u32 val; + struct nvgpu_posix_io_callbacks *old_io; + struct nvgpu_posix_io_callbacks new_io = { + .readl = readl_access_reg_fn, + .writel = writel_access_reg_fn + }; + + old_io = nvgpu_posix_register_io(g, &new_io); + + gv11b_fifo_intr_0_enable(g, true); + intr_en_0 = nvgpu_posix_io_readl_reg_space(g, fifo_intr_en_0_r()); + assert((intr_en_0 & fifo_intr_0_ctxsw_timeout_pending_f()) != 0); + + nvgpu_posix_io_writel_reg_space(g, + fifo_intr_ctxsw_timeout_r(), 0xcafe); + gv11b_fifo_intr_set_recover_mask(g); + intr_en_0 = nvgpu_posix_io_readl_reg_space(g, fifo_intr_en_0_r()); + assert((intr_en_0 & fifo_intr_0_ctxsw_timeout_pending_f()) == 0); + val = nvgpu_posix_io_readl_reg_space(g, fifo_intr_ctxsw_timeout_r()); + assert(val == 0); + + gv11b_fifo_intr_unset_recover_mask(g); + intr_en_0 = nvgpu_posix_io_readl_reg_space(g, fifo_intr_en_0_r()); + assert((intr_en_0 & fifo_intr_0_ctxsw_timeout_pending_f()) != 0); + + ret = UNIT_SUCCESS; +done: + (void) nvgpu_posix_register_io(g, old_io); + return ret; +} \ No newline at end of file diff --git a/userspace/units/fifo/fifo/gv11b/nvgpu-fifo-intr-gv11b.h b/userspace/units/fifo/fifo/gv11b/nvgpu-fifo-intr-gv11b.h new file mode 100644 index 000000000..d5fc1469b --- /dev/null +++ b/userspace/units/fifo/fifo/gv11b/nvgpu-fifo-intr-gv11b.h @@ -0,0 +1,145 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef UNIT_NVGPU_FIFO_INTR_GV11B_H +#define UNIT_NVGPU_FIFO_INTR_GV11B_H + +#include + +struct unit_module; +struct gk20a; + +/** @addtogroup SWUTS-fifo-fifo-gv11b + * @{ + * + * Software Unit Test Specification for fifo/fifo/gv11b + */ + +/** + * Test specification for: test_gv11b_fifo_intr_0_enable + * + * Description: Enable stalling interrupts + * + * Test Type: Feature based + * + * Targets: gv11b_fifo_intr_0_enable + * + * Input: test_fifo_init_support() run for this GPU + * + * Steps: + * - Check enabling of interrupts: + * - Check that fifo ctxsw_timeout is enabled. + * - Check that pbdma interrupts are enabled. + * - Check that runlist interrupts are cleared (~0 written to + * fifo_intr_runlist_r). + * - Check that fifo interrupts are cleared (~0 written to fifo_intr_0_r). + * - Check that fifo interrupt enable mask is non-zero. + * - Check disabling of interrupts: + * - Check that fifo ctxsw_timeout is disabled. + * - Check that pbdma interrupts are disabled. + * - Check that fifo interrupt enable mask is zero. + * + * Output: Returns PASS if all branches gave expected results. FAIL otherwise. + */ +int test_gv11b_fifo_intr_0_enable(struct unit_module *m, + struct gk20a *g, void *args); + +/** + * Test specification for: test_gv11b_fifo_handle_sched_error + * + * Description: Handle scheduling error + * + * Test Type: Feature based + * + * Targets: gv11b_fifo_handle_sched_error + * + * Input: test_fifo_init_support() run for this GPU + * + * Steps: + * - Set fifo_intr_sched_error_r with sched error code. + * - Call gv11b_fifo_handle_sched_error. + * - Check for valid sched error codes SCHED_ERROR_CODE_RL_REQ_TIMEOUT and + * SCHED_ERROR_CODE_BAD_TSG. + * - Check for invalid sched error code (outside expected range). + * + * Output: Returns PASS if all branches gave expected results. FAIL otherwise. + */ +int test_gv11b_fifo_handle_sched_error(struct unit_module *m, + struct gk20a *g, void *args); + +/** + * Test specification for: test_gv11b_fifo_intr_0_isr + * + * Description: Stalling interrupt handler + * + * Test Type: Feature based + * + * Targets: gv11b_fifo_intr_0_isr + * + * Input: test_fifo_init_support() run for this GPU + * + * Steps: + * - Install register io callbacks to emulate clearing of interrupts + * (write to fifo_intr_0 clears interrupts). + * - Set fifo_intr_0 with all combinations of handled interrupts, as + * well as one unhandled interrupt. + * - Check that gv11b_fifo_intr_0_isr clears interrupts for all handled + * interrupts. + * - Check that, when g->fifo.sw_ready is false, gv11b_fifo_intr_0_isr + * clears any pending interrupt. + * + * Output: Returns PASS if all branches gave expected results. FAIL otherwise. + */ +int test_gv11b_fifo_intr_0_isr(struct unit_module *m, + struct gk20a *g, void *args); + +/** + * Test specification for: test_gv11b_fifo_intr_recover_mask + * + * Description: Set/unset recovery mask + * + * Test Type: Feature based + * + * Targets: gv11b_fifo_intr_set_recover_mask, gv11b_fifo_intr_unset_recover_mask + * + * Input: test_fifo_init_support() run for this GPU + * + * Steps: + * - Install register io callbacks to emulate clearing of the mask of + * engines that timed out (write to fifo_intr_ctxsw_timeout_r clears mask). + * - Enable interrupts with gv11b_fifo_intr_0_enable, and make sure that + * ctxsw_timeout interrupt is enabled. + * - Call gv11b_fifo_intr_set_recover_mask, and check that: + * - ctxsw_timeout interrupt is disabled in fifo_intr_en_0_r. + * - fifo_intr_ctxsw_timeout_r has been cleared. + * - Call gv11b_fifo_intr_unset_recover_mask, and check that: + * - ctxsw_timeout interrupt is enabled in fifo_intr_en_0_r. + * + * Output: Returns PASS if all branches gave expected results. FAIL otherwise. + */ +int test_gv11b_fifo_intr_recover_mask(struct unit_module *m, + struct gk20a *g, void *args); + +/** + * @} + */ + +#endif /* UNIT_NVGPU_FIFO_INTR_GV11B_H */