diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga100.c b/drivers/gpu/nvgpu/hal/init/hal_ga100.c index 6d9cbe7fe..7203a0531 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_ga100.c +++ b/drivers/gpu/nvgpu/hal/init/hal_ga100.c @@ -1508,6 +1508,8 @@ static const struct gops_mc ga100_ops_mc = { #ifdef CONFIG_NVGPU_HAL_NON_FUSA .intr_get_unit_info = ga10b_mc_intr_get_unit_info, #endif + .get_eng_stall_base_vector = ga10b_intr_get_eng_stall_base_vector, + .get_eng_nonstall_base_vector = ga10b_intr_get_eng_nonstall_base_vector, }; #endif diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c index 6be031793..9b0be3ea1 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c @@ -1540,6 +1540,8 @@ static const struct gops_mc ga10b_ops_mc = { .ltc_isr = mc_tu104_ltc_isr, .is_mmu_fault_pending = ga10b_intr_is_mmu_fault_pending, .intr_get_unit_info = ga10b_mc_intr_get_unit_info, + .get_eng_nonstall_base_vector = ga10b_intr_get_eng_nonstall_base_vector, + .get_eng_stall_base_vector = ga10b_intr_get_eng_stall_base_vector, }; static const struct gops_debug ga10b_ops_debug = { diff --git a/drivers/gpu/nvgpu/hal/mc/mc_intr_ga10b.h b/drivers/gpu/nvgpu/hal/mc/mc_intr_ga10b.h index 9def9510d..b009c1cdd 100644 --- a/drivers/gpu/nvgpu/hal/mc/mc_intr_ga10b.h +++ b/drivers/gpu/nvgpu/hal/mc/mc_intr_ga10b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -43,6 +43,8 @@ void ga10b_intr_stall_pause(struct gk20a *g); void ga10b_intr_stall_resume(struct gk20a *g); void ga10b_intr_isr_stall(struct gk20a *g); +u32 ga10b_intr_get_eng_nonstall_base_vector(struct gk20a *g); +u32 ga10b_intr_get_eng_stall_base_vector(struct gk20a *g); bool ga10b_intr_is_stall_and_eng_intr_pending(struct gk20a *g, u32 engine_id, u32 *eng_intr_pending); bool ga10b_mc_intr_get_unit_info(struct gk20a *g, u32 unit); diff --git a/drivers/gpu/nvgpu/hal/mc/mc_intr_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/mc/mc_intr_ga10b_fusa.c index c247d7fe5..c4c210552 100644 --- a/drivers/gpu/nvgpu/hal/mc/mc_intr_ga10b_fusa.c +++ b/drivers/gpu/nvgpu/hal/mc/mc_intr_ga10b_fusa.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2021-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -322,9 +322,23 @@ void ga10b_intr_mask_top(struct gk20a *g) } } +u32 ga10b_intr_get_eng_nonstall_base_vector(struct gk20a *g) +{ + u32 reg_val = + nvgpu_readl(g, ctrl_legacy_engine_nonstall_intr_base_vectorid_r()); + return ctrl_legacy_engine_nonstall_intr_base_vectorid_vector_v(reg_val); +} + +u32 ga10b_intr_get_eng_stall_base_vector(struct gk20a *g) +{ + u32 reg_val = + nvgpu_readl(g, ctrl_legacy_engine_stall_intr_base_vectorid_r()); + return ctrl_legacy_engine_stall_intr_base_vectorid_vector_v(reg_val); +} + bool ga10b_mc_intr_get_unit_info(struct gk20a *g, u32 unit) { - u32 vectorid, reg_val, i; + u32 vectorid, i; struct nvgpu_intr_unit_info *intr_unit_info; u64 tmp_subtree_mask = 0ULL; @@ -373,10 +387,7 @@ bool ga10b_mc_intr_get_unit_info(struct gk20a *g, u32 unit) * is because engine interrupt mask is being used to configure * interrupts. Base vector is read from ctrl reg. */ - reg_val = nvgpu_readl(g, - ctrl_legacy_engine_nonstall_intr_base_vectorid_r()); - vectorid = - ctrl_legacy_engine_nonstall_intr_base_vectorid_vector_v(reg_val); + vectorid = g->ops.mc.get_eng_nonstall_base_vector(g); intr_unit_info->vectorid[0] = vectorid; intr_unit_info->vectorid_size = NVGPU_CIC_INTR_VECTORID_SIZE_ONE; @@ -398,10 +409,7 @@ bool ga10b_mc_intr_get_unit_info(struct gk20a *g, u32 unit) break; #endif case NVGPU_CIC_INTR_UNIT_GR_STALL: - reg_val = nvgpu_readl(g, - ctrl_legacy_engine_stall_intr_base_vectorid_r()); - vectorid = - ctrl_legacy_engine_stall_intr_base_vectorid_vector_v(reg_val); + vectorid = g->ops.mc.get_eng_stall_base_vector(g); intr_unit_info->vectorid[0] = vectorid; intr_unit_info->vectorid_size = NVGPU_CIC_INTR_VECTORID_SIZE_ONE; @@ -417,10 +425,7 @@ bool ga10b_mc_intr_get_unit_info(struct gk20a *g, u32 unit) return true; case NVGPU_CIC_INTR_UNIT_CE_STALL: - reg_val = nvgpu_readl(g, - ctrl_legacy_engine_stall_intr_base_vectorid_r()); - vectorid = - ctrl_legacy_engine_stall_intr_base_vectorid_vector_v(reg_val); + vectorid = g->ops.mc.get_eng_stall_base_vector(g); intr_unit_info->vectorid[0] = vectorid; intr_unit_info->vectorid_size = NVGPU_CIC_INTR_VECTORID_SIZE_ONE; @@ -1047,13 +1052,10 @@ static bool ga10b_intr_is_eng_stall_pending(struct gk20a *g, u32 engine_id) u64 eng_subtree_mask = 0ULL; u64 subtree_mask = 0ULL; u32 intr_leaf0, intr_leaf1; - u32 reg_val, vectorid; + u32 vectorid; bool eng_stall_pending = false; - reg_val = nvgpu_readl(g, - ctrl_legacy_engine_stall_intr_base_vectorid_r()); - vectorid = - ctrl_legacy_engine_stall_intr_base_vectorid_vector_v(reg_val); + vectorid = g->ops.mc.get_eng_stall_base_vector(g); eng_subtree_mask = ((u64)nvgpu_engine_act_interrupt_mask(g, engine_id)); eng_subtree_mask <<= GPU_VECTOR_TO_LEAF_SHIFT(vectorid); diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/mc.h b/drivers/gpu/nvgpu/include/nvgpu/gops/mc.h index d42fc0010..645b1e4e7 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops/mc.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/mc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -301,6 +301,32 @@ struct gops_mc { */ void (*gr1_out_of_reset)(struct gk20a *g, u32 devtype, bool enable); + /** + * @brief Retrieve the base vector for engine non-stall interrupts. + * + * @param g [in] The GPU driver struct. + * + * This function is invoked to get the base vector for engine non-stall + * interrupts. An engine's non-stall interrupt vector is the sum of this + * base vector and the engine's interrupt ID. + * + * @return the base vector for engine non-stall interrupts. + */ + u32 (*get_eng_nonstall_base_vector)(struct gk20a *g); + + /** + * @brief Retrieve the base vector for engine stall interrupts. + * + * @param g [in] The GPU driver struct. + * + * This function is invoked to get the base vector for engine stall + * interrupts. An engine's stall interrupt vector is the sum of this + * base vector and the engine's interrupt ID. + * + * @return the base vector for engine stall interrupts. + */ + u32 (*get_eng_stall_base_vector)(struct gk20a *g); + /** @endcond DOXYGEN_SHOULD_SKIP_THIS */ };