gpu: nvgpu: Initialize FECS explicitly on recovery

Instead of calling second phase of PMU boot sequence, initialize FECS
directly.

Change-Id: I7f9de0c5ec42049033839d244979f3f3daabf317
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/410204

drivers/gpu/nvgpu/gk20a/fifo_gk20a.c

@@ -831,9 +831,6 @@ static void gk20a_fifo_handle_mmu_fault_thread(struct work_struct *work)
 	struct gk20a *g = f->g;
 	int i;
 
-	/* Reinitialise FECS and GR */
-	gk20a_init_pmu_setup_hw2(g);
-
 	/* It is safe to enable ELPG again. */
 	gk20a_pmu_enable_elpg(g);
 

drivers/gpu/nvgpu/gk20a/gr_gk20a.c

@@ -4771,15 +4771,47 @@ static void gk20a_gr_set_alpha_circular_buffer_size(struct gk20a *g, u32 data)
 	}
 }
 
-void gk20a_gr_reset(struct gk20a *g)
+int gk20a_gr_reset(struct gk20a *g)
 {
 	int err;
+	u32 size;
+
 	err = gk20a_init_gr_prepare(g);
-	BUG_ON(err);
+	if (err)
+		return err;
+
 	err = gk20a_init_gr_reset_enable_hw(g);
-	BUG_ON(err);
+	if (err)
+		return err;
+
 	err = gk20a_init_gr_setup_hw(g);
-	BUG_ON(err);
+	if (err)
+		return err;
+
+	size = 0;
+	err = gr_gk20a_fecs_get_reglist_img_size(g, &size);
+	if (err) {
+		gk20a_err(dev_from_gk20a(g),
+			"fail to query fecs pg buffer size");
+		return err;
+	}
+
+	err = gr_gk20a_fecs_set_reglist_bind_inst(g,
+			g->mm.pmu.inst_block.cpu_pa);
+	if (err) {
+		gk20a_err(dev_from_gk20a(g),
+			"fail to bind pmu inst to gr");
+		return err;
+	}
+
+	err = gr_gk20a_fecs_set_reglist_virtual_addr(g, g->pmu.pg_buf.pmu_va);
+	if (err) {
+		gk20a_err(dev_from_gk20a(g),
+			"fail to set pg buffer pmu va");
+		return err;
+	}
+
+	return 0;
 }
 
 static int gr_gk20a_handle_sw_method(struct gk20a *g, u32 addr,
@@ -5511,7 +5543,7 @@ int gr_gk20a_fecs_set_reglist_bind_inst(struct gk20a *g, phys_addr_t addr)
 			   .mailbox.fail = 0});
 }
 
-int gr_gk20a_fecs_set_reglist_virual_addr(struct gk20a *g, u64 pmu_va)
+int gr_gk20a_fecs_set_reglist_virtual_addr(struct gk20a *g, u64 pmu_va)
 {
 	return gr_gk20a_submit_fecs_method_op(g,
 		   (struct fecs_method_op_gk20a) {

drivers/gpu/nvgpu/gk20a/gr_gk20a.h

@@ -314,7 +314,7 @@ struct gk20a_ctxsw_bootloader_desc {
 struct gpu_ops;
 void gk20a_init_gr(struct gpu_ops *gops);
 int gk20a_init_gr_support(struct gk20a *g);
-void gk20a_gr_reset(struct gk20a *g);
+int gk20a_gr_reset(struct gk20a *g);
 
 int gk20a_init_gr_channel(struct channel_gk20a *ch_gk20a);
 
@@ -351,7 +351,7 @@ int gr_gk20a_load_zbc_default_table(struct gk20a *g, struct gr_gk20a *gr);
 /* pmu */
 int gr_gk20a_fecs_get_reglist_img_size(struct gk20a *g, u32 *size);
 int gr_gk20a_fecs_set_reglist_bind_inst(struct gk20a *g, phys_addr_t addr);
-int gr_gk20a_fecs_set_reglist_virual_addr(struct gk20a *g, u64 pmu_va);
+int gr_gk20a_fecs_set_reglist_virtual_addr(struct gk20a *g, u64 pmu_va);
 
 void gr_gk20a_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine);
 void gr_gk20a_init_blcg_mode(struct gk20a *g, u32 mode, u32 engine);

drivers/gpu/nvgpu/gk20a/pmu_gk20a.c

@@ -1882,7 +1882,7 @@ int gk20a_init_pmu_setup_hw2(struct gk20a *g)
 		return err;
 	}
 
-	err = gr_gk20a_fecs_set_reglist_virual_addr(g, pmu->pg_buf.pmu_va);
+	err = gr_gk20a_fecs_set_reglist_virtual_addr(g, pmu->pg_buf.pmu_va);
 	if (err) {
 		gk20a_err(dev_from_gk20a(g),
 			"fail to set pg buffer pmu va");