From 2506dd2b866934dfc8ebcfbdcbf43c9f91f4b2d0 Mon Sep 17 00:00:00 2001 From: mkumbar Date: Tue, 29 Mar 2022 12:47:09 +0530 Subject: [PATCH] gpu: nvgpu: set ACR FW load flag as per platform -Add ACR FW load flag which will be set based on platform and load the requested FW accordingly. Bug 3572869 Change-Id: I6643f183fed104fef059dd691036a2c509073a50 Signed-off-by: mkumbar Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2689022 Reviewed-by: svcacv Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-misra Reviewed-by: svc-mobile-cert Reviewed-by: Deepak Nibade GVS: Gerrit_Virtual_Submit Tested-by: Andy Chiang --- drivers/gpu/nvgpu/common/acr/acr.c | 17 +++++++++- .../gpu/nvgpu/common/acr/acr_blob_construct.c | 32 +++++++++---------- drivers/gpu/nvgpu/common/acr/acr_bootstrap.c | 26 ++++----------- drivers/gpu/nvgpu/common/acr/acr_priv.h | 1 + 4 files changed, 40 insertions(+), 36 deletions(-) diff --git a/drivers/gpu/nvgpu/common/acr/acr.c b/drivers/gpu/nvgpu/common/acr/acr.c index 0fec2dff8..bf68ed99f 100644 --- a/drivers/gpu/nvgpu/common/acr/acr.c +++ b/drivers/gpu/nvgpu/common/acr/acr.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -172,6 +172,21 @@ int nvgpu_acr_init(struct gk20a *g) break; } + /* + * Firmware is stored in soc specific path in FMODEL + * Hence NVGPU_REQUEST_FIRMWARE_NO_WARN is used instead + * of NVGPU_REQUEST_FIRMWARE_NO_SOC + */ + if (err == 0) { +#ifdef CONFIG_NVGPU_SIM + if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { + g->acr->fw_load_flag = NVGPU_REQUEST_FIRMWARE_NO_WARN; + } else +#endif + { + g->acr->fw_load_flag = NVGPU_REQUEST_FIRMWARE_NO_SOC; + } + } done: return err; } diff --git a/drivers/gpu/nvgpu/common/acr/acr_blob_construct.c b/drivers/gpu/nvgpu/common/acr/acr_blob_construct.c index 89f7c9d1c..cfb7d2bdf 100644 --- a/drivers/gpu/nvgpu/common/acr/acr_blob_construct.c +++ b/drivers/gpu/nvgpu/common/acr/acr_blob_construct.c @@ -182,29 +182,29 @@ int nvgpu_acr_lsf_fecs_ucode_details(struct gk20a *g, void *lsf_ucode_img) switch (ver) { case NVGPU_GPUID_GV11B: fecs_sig = nvgpu_request_firmware(g, GM20B_FECS_UCODE_SIG, - NVGPU_REQUEST_FIRMWARE_NO_WARN); + g->acr->fw_load_flag); break; case NVGPU_GPUID_GA10B: if (!nvgpu_is_enabled(g, NVGPU_PKC_LS_SIG_ENABLED)) { fecs_sig = nvgpu_request_firmware(g, GM20B_FECS_UCODE_SIG, - NVGPU_REQUEST_FIRMWARE_NO_WARN); + g->acr->fw_load_flag); } else { fecs_sig = nvgpu_request_firmware(g, GA10B_FECS_UCODE_PKC_SIG, - NVGPU_REQUEST_FIRMWARE_NO_WARN); + g->acr->fw_load_flag); } break; #ifdef CONFIG_NVGPU_DGPU case NVGPU_GPUID_TU104: fecs_sig = nvgpu_request_firmware(g, TU104_FECS_UCODE_SIG, - NVGPU_REQUEST_FIRMWARE_NO_SOC); + g->acr->fw_load_flag); break; #endif #if defined(CONFIG_NVGPU_NON_FUSA) case NVGPU_GPUID_GA100: fecs_sig = nvgpu_request_firmware(g, GA100_FECS_UCODE_SIG, - NVGPU_REQUEST_FIRMWARE_NO_SOC); + g->acr->fw_load_flag); break; #endif @@ -325,29 +325,29 @@ int nvgpu_acr_lsf_gpccs_ucode_details(struct gk20a *g, void *lsf_ucode_img) switch (ver) { case NVGPU_GPUID_GV11B: gpccs_sig = nvgpu_request_firmware(g, T18x_GPCCS_UCODE_SIG, - NVGPU_REQUEST_FIRMWARE_NO_WARN); + g->acr->fw_load_flag); break; case NVGPU_GPUID_GA10B: if (!nvgpu_is_enabled(g, NVGPU_PKC_LS_SIG_ENABLED)) { gpccs_sig = nvgpu_request_firmware(g, T18x_GPCCS_UCODE_SIG, - NVGPU_REQUEST_FIRMWARE_NO_WARN); + g->acr->fw_load_flag); } else { gpccs_sig = nvgpu_request_firmware(g, GA10B_GPCCS_UCODE_PKC_SIG, - NVGPU_REQUEST_FIRMWARE_NO_WARN); + g->acr->fw_load_flag); } break; #ifdef CONFIG_NVGPU_DGPU case NVGPU_GPUID_TU104: gpccs_sig = nvgpu_request_firmware(g, TU104_GPCCS_UCODE_SIG, - NVGPU_REQUEST_FIRMWARE_NO_SOC); + g->acr->fw_load_flag); break; #endif #if defined(CONFIG_NVGPU_NON_FUSA) case NVGPU_GPUID_GA100: gpccs_sig = nvgpu_request_firmware(g, GA100_GPCCS_UCODE_SIG, - NVGPU_REQUEST_FIRMWARE_NO_SOC); + g->acr->fw_load_flag); break; #endif @@ -469,11 +469,11 @@ int nvgpu_acr_lsf_sec2_ucode_details(struct gk20a *g, void *lsf_ucode_img) if (g->is_fusa_sku) { sec2_fw = nvgpu_request_firmware(g, LSF_SEC2_UCODE_IMAGE_FUSA_BIN, - NVGPU_REQUEST_FIRMWARE_NO_SOC); + g->acr->fw_load_flag); } else { sec2_fw = nvgpu_request_firmware(g, LSF_SEC2_UCODE_IMAGE_BIN, - NVGPU_REQUEST_FIRMWARE_NO_SOC); + g->acr->fw_load_flag); } if (sec2_fw == NULL) { @@ -487,11 +487,11 @@ int nvgpu_acr_lsf_sec2_ucode_details(struct gk20a *g, void *lsf_ucode_img) if (g->is_fusa_sku) { sec2_desc = nvgpu_request_firmware(g, LSF_SEC2_UCODE_DESC_FUSA_BIN, - NVGPU_REQUEST_FIRMWARE_NO_SOC); + g->acr->fw_load_flag); } else { sec2_desc = nvgpu_request_firmware(g, LSF_SEC2_UCODE_DESC_BIN, - NVGPU_REQUEST_FIRMWARE_NO_SOC); + g->acr->fw_load_flag); } if (sec2_desc == NULL) { @@ -505,11 +505,11 @@ int nvgpu_acr_lsf_sec2_ucode_details(struct gk20a *g, void *lsf_ucode_img) if (g->is_fusa_sku) { sec2_sig = nvgpu_request_firmware(g, LSF_SEC2_UCODE_SIG_FUSA_BIN, - NVGPU_REQUEST_FIRMWARE_NO_SOC); + g->acr->fw_load_flag); } else { sec2_sig = nvgpu_request_firmware(g, LSF_SEC2_UCODE_SIG_BIN, - NVGPU_REQUEST_FIRMWARE_NO_SOC); + g->acr->fw_load_flag); } if (sec2_sig == NULL) { nvgpu_err(g, "failed to load SEC2 sig!!"); diff --git a/drivers/gpu/nvgpu/common/acr/acr_bootstrap.c b/drivers/gpu/nvgpu/common/acr/acr_bootstrap.c index 4985e69ce..eaffcd2ef 100644 --- a/drivers/gpu/nvgpu/common/acr/acr_bootstrap.c +++ b/drivers/gpu/nvgpu/common/acr/acr_bootstrap.c @@ -246,22 +246,10 @@ int nvgpu_acr_bootstrap_hs_ucode(struct gk20a *g, struct nvgpu_acr *acr, return err; } } else { - /* Firmware is stored in soc specific path in FMODEL - * Hence NVGPU_REQUEST_FIRMWARE_NO_WARN is used instead - * of NVGPU_REQUEST_FIRMWARE_NO_SOC - */ -#ifdef CONFIG_NVGPU_SIM - if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { - acr_fw = nvgpu_request_firmware(g, - acr_desc->acr_fw_name, - NVGPU_REQUEST_FIRMWARE_NO_WARN); - } else -#endif - { - acr_fw = nvgpu_request_firmware(g, - acr_desc->acr_fw_name, - NVGPU_REQUEST_FIRMWARE_NO_SOC); - } + acr_fw = nvgpu_request_firmware(g, + acr_desc->acr_fw_name, + g->acr->fw_load_flag); + if (acr_fw == NULL) { nvgpu_err(g, "%s ucode get fail for %s", acr_desc->acr_fw_name, g->name); @@ -334,7 +322,7 @@ static int ga10b_load_riscv_acr_ucodes(struct gk20a *g, struct hs_acr *acr) nvgpu_acr_dbg(g, "loading ACR's manifest bin\n"); acr->manifest_fw = nvgpu_request_firmware(g, acr->acr_manifest_name, - NVGPU_REQUEST_FIRMWARE_NO_WARN); + g->acr->fw_load_flag); if (acr->manifest_fw == NULL) { nvgpu_err(g, "%s ucode get fail for %s", acr->acr_manifest_name, g->name); @@ -344,7 +332,7 @@ static int ga10b_load_riscv_acr_ucodes(struct gk20a *g, struct hs_acr *acr) nvgpu_acr_dbg(g, "loading ACR's text bin\n"); acr->code_fw = nvgpu_request_firmware(g, acr->acr_code_name, - NVGPU_REQUEST_FIRMWARE_NO_WARN); + g->acr->fw_load_flag); if (acr->code_fw == NULL) { nvgpu_err(g, "%s ucode get fail for %s", acr->acr_code_name, g->name); @@ -355,7 +343,7 @@ static int ga10b_load_riscv_acr_ucodes(struct gk20a *g, struct hs_acr *acr) nvgpu_acr_dbg(g, "loading ACR's data bin\n"); acr->data_fw = nvgpu_request_firmware(g, acr->acr_data_name, - NVGPU_REQUEST_FIRMWARE_NO_WARN); + g->acr->fw_load_flag); if (acr->data_fw == NULL) { nvgpu_err(g, "%s ucode get fail for %s", acr->acr_data_name, g->name); diff --git a/drivers/gpu/nvgpu/common/acr/acr_priv.h b/drivers/gpu/nvgpu/common/acr/acr_priv.h index a454830d6..1dda2005b 100644 --- a/drivers/gpu/nvgpu/common/acr/acr_priv.h +++ b/drivers/gpu/nvgpu/common/acr/acr_priv.h @@ -130,6 +130,7 @@ struct acr_lsf_config { struct nvgpu_acr { struct gk20a *g; + u32 fw_load_flag; u32 bootstrap_owner; u32 num_of_sig;