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gpu: nvgpu: enable platform atomic feature

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Support following changes related to platform atomic feature
NV_PFB_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE to RMW MODE
NV_PFB_PRI_MMU_CTRL_ATOMIC_CAPABILITY_SYS_NCOH_MODE to L2
NV_PFB_HSHUB_NUM_ACTIVE_LTCS_HUB_SYS_ATOMIC_MODE to USE_RMW
NV_PFB_FBHUB_NUM_ACTIVE_LTCS_HUB_SYS_ATOMIC_MODE to USE_RMW
NV_PFB_FBHUB_NUM_ACTIVE_LTCS_HUB_SYS_NCOH_ATOMIC_MODE to USE_READ

In gv11b, FBHUB_NUM_ACTIVE_LTCS register has read only privilege,
so atomic mode register bits cannot be updated from kernel code.

atomic capability and atomic_sys_ncoh_mode bits are copied from
fb mmu_ctrl to gpcs_mmu_ctrl register.

new tu104 hal for fb_enable_nvlink function.

Change-Id: Ia78986c1c56795c6efad20f4ba42700ef1c2c1ad
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2013481
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vinod G
2019-02-06 16:23:11 -08:00
committed by mobile promotions
parent 9e0a9004b7
commit 251e3eaa80
8 changed files with 151 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

30
drivers/gpu/nvgpu/common/fb/fb_gv11b.c
View File

@@ -82,6 +82,34 @@ static void gv11b_init_nvlink_soc_credits(struct gk20a *g)
}
}
static void gv11b_fb_set_atomic_mode(struct gk20a *g)
{
u32 reg_val;
/*
* NV_PFB_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE to RMW MODE
* NV_PFB_PRI_MMU_CTRL_ATOMIC_CAPABILITY_SYS_NCOH_MODE to L2
*/
reg_val = nvgpu_readl(g, fb_mmu_ctrl_r());
reg_val = set_field(reg_val, fb_mmu_ctrl_atomic_capability_mode_m(),
fb_mmu_ctrl_atomic_capability_mode_rmw_f());
reg_val = set_field(reg_val, fb_mmu_ctrl_atomic_capability_sys_ncoh_mode_m(),
fb_mmu_ctrl_atomic_capability_sys_ncoh_mode_l2_f());
nvgpu_writel(g, fb_mmu_ctrl_r(), reg_val);
/* NV_PFB_HSHUB_NUM_ACTIVE_LTCS_HUB_SYS_ATOMIC_MODE to USE_RMW */
reg_val = nvgpu_readl(g, fb_hshub_num_active_ltcs_r());
reg_val = set_field(reg_val, fb_hshub_num_active_ltcs_hub_sys_atomic_mode_m(),
fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_f());
nvgpu_writel(g, fb_hshub_num_active_ltcs_r(), reg_val);
nvgpu_log(g, gpu_dbg_info, "fb_mmu_ctrl_r 0x%x",
gk20a_readl(g, fb_mmu_ctrl_r()));
nvgpu_log(g, gpu_dbg_info, "fb_hshub_num_active_ltcs_r 0x%x",
gk20a_readl(g, fb_hshub_num_active_ltcs_r()));
}
void gv11b_fb_init_hw(struct gk20a *g)
{
gm20b_fb_init_hw(g);
@@ -95,6 +123,8 @@ void gv11b_fb_init_fs_state(struct gk20a *g)
gv11b_init_nvlink_soc_credits(g);
gv11b_fb_set_atomic_mode(g);
nvgpu_log(g, gpu_dbg_info, "fbhub active ltcs %x",
gk20a_readl(g, fb_fbhub_num_active_ltcs_r()));

29
drivers/gpu/nvgpu/common/fb/fb_tu104.c
View File

@@ -595,3 +595,32 @@ size_t tu104_fb_get_vidmem_size(struct gk20a *g)
return bytes;
}
int tu104_fb_enable_nvlink(struct gk20a *g)
{
int ret = 0;
u32 data;
nvgpu_log(g, gpu_dbg_nvlink|gpu_dbg_info, "enabling nvlink");
ret = gv100_fb_enable_nvlink(g);
if (ret != 0) {
return ret;
}
/* NV_PFB_PRI_MMU_CTRL_ATOMIC_CAPABILITY_SYS_NCOH_MODE to L2 */
data = nvgpu_readl(g, fb_mmu_ctrl_r());
data = set_field(data, fb_mmu_ctrl_atomic_capability_sys_ncoh_mode_m(),
fb_mmu_ctrl_atomic_capability_sys_ncoh_mode_l2_f());
nvgpu_writel(g, fb_mmu_ctrl_r(), data);
/* NV_PFB_FBHUB_NUM_ACTIVE_LTCS_HUB_SYS_NCOH_ATOMIC_MODE to USE_READ */
data = nvgpu_readl(g, fb_fbhub_num_active_ltcs_r());
data = set_field(data,
fb_fbhub_num_active_ltcs_hub_sys_ncoh_atomic_mode_m(),
fb_fbhub_num_active_ltcs_hub_sys_ncoh_atomic_mode_use_read_f());
nvgpu_writel(g, fb_fbhub_num_active_ltcs_r(), data);
return ret;
}

3
drivers/gpu/nvgpu/common/fb/fb_tu104.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -59,5 +59,6 @@ void fb_tu104_init_cbc(struct gk20a *g, struct gr_gk20a *gr);
int tu104_fb_apply_pdb_cache_war(struct gk20a *g);
size_t tu104_fb_get_vidmem_size(struct gk20a *g);
int tu104_fb_enable_nvlink(struct gk20a *g);
#endif /* NVGPU_FB_TU104_H */

4
drivers/gpu/nvgpu/gv11b/gr_gv11b.c
View File

@@ -4262,7 +4262,9 @@ void gr_gv11b_init_gpc_mmu(struct gk20a *g)
gr_gpcs_pri_mmu_ctrl_cache_mode_m() |
gr_gpcs_pri_mmu_ctrl_mmu_aperture_m() |
gr_gpcs_pri_mmu_ctrl_mmu_vol_m() |
gr_gpcs_pri_mmu_ctrl_mmu_disable_m();
gr_gpcs_pri_mmu_ctrl_mmu_disable_m()|
gr_gpcs_pri_mmu_ctrl_atomic_capability_mode_m()|
gr_gpcs_pri_mmu_ctrl_atomic_capability_sys_ncoh_mode_m();
gk20a_writel(g, gr_gpcs_pri_mmu_ctrl_r(), temp);
gk20a_writel(g, gr_gpcs_pri_mmu_pm_unit_mask_r(), 0);
gk20a_writel(g, gr_gpcs_pri_mmu_pm_req_mask_r(), 0);

54
drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -62,6 +62,22 @@ static inline u32 fb_fbhub_num_active_ltcs_r(void)
{
return 0x00100800U;
}
static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_m(void)
{
return U32(0x1U) << 25U;
}
static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_f(void)
{
return 0x2000000U;
}
static inline u32 fb_fbhub_num_active_ltcs_hub_sys_ncoh_atomic_mode_m(void)
{
return U32(0x1U) << 26U;
}
static inline u32 fb_fbhub_num_active_ltcs_hub_sys_ncoh_atomic_mode_use_read_f(void)
{
return 0x0U;
}
static inline u32 fb_mmu_ctrl_r(void)
{
return 0x00100c80U;
@@ -78,6 +94,42 @@ static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r)
{
return (r >> 16U) & 0xffU;
}
static inline u32 fb_mmu_ctrl_atomic_capability_mode_m(void)
{
return U32(0x3U) << 24U;
}
static inline u32 fb_mmu_ctrl_atomic_capability_mode_l2_f(void)
{
return 0x0U;
}
static inline u32 fb_mmu_ctrl_atomic_capability_mode_rmw_f(void)
{
return 0x2000000U;
}
static inline u32 fb_mmu_ctrl_atomic_capability_sys_ncoh_mode_m(void)
{
return U32(0x1U) << 27U;
}
static inline u32 fb_mmu_ctrl_atomic_capability_sys_ncoh_mode_l2_f(void)
{
return 0x0U;
}
static inline u32 fb_hshub_num_active_ltcs_r(void)
{
return 0x001fbc20U;
}
static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_m(void)
{
return U32(0x1U) << 25U;
}
static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_read_f(void)
{
return 0x0U;
}
static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_f(void)
{
return 0x2000000U;
}
static inline u32 fb_priv_mmu_phy_secure_r(void)
{
return 0x00100ce4U;

10
drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -4978,6 +4978,14 @@ static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_disable_m(void)
{
return U32(0x1U) << 31U;
}
static inline u32 gr_gpcs_pri_mmu_ctrl_atomic_capability_mode_m(void)
{
return U32(0x3U) << 24U;
}
static inline u32 gr_gpcs_pri_mmu_ctrl_atomic_capability_sys_ncoh_mode_m(void)
{
return U32(0x1U) << 27U;
}
static inline u32 gr_gpcs_pri_mmu_pm_unit_mask_r(void)
{
return 0x00418890U;

18
drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_fb_tu104.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -138,6 +138,14 @@ static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_f(void)
{
return 0x2000000U;
}
static inline u32 fb_fbhub_num_active_ltcs_hub_sys_ncoh_atomic_mode_m(void)
{
return U32(0x1U) << 26U;
}
static inline u32 fb_fbhub_num_active_ltcs_hub_sys_ncoh_atomic_mode_use_read_f(void)
{
return 0x0U;
}
static inline u32 fb_mmu_ctrl_r(void)
{
return 0x00100c80U;
@@ -198,6 +206,14 @@ static inline u32 fb_mmu_ctrl_atomic_capability_mode_power_f(void)
{
return 0x3000000U;
}
static inline u32 fb_mmu_ctrl_atomic_capability_sys_ncoh_mode_m(void)
{
return U32(0x1U) << 27U;
}
static inline u32 fb_mmu_ctrl_atomic_capability_sys_ncoh_mode_l2_f(void)
{
return 0x0U;
}
static inline u32 fb_mmu_bind_imb_r(void)
{
return 0x00100cacU;

8
drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_gr_tu104.h
View File

@@ -4006,6 +4006,14 @@ static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_disable_m(void)
{
return U32(0x1U) << 31U;
}
static inline u32 gr_gpcs_pri_mmu_ctrl_atomic_capability_mode_m(void)
{
return U32(0x3U) << 24U;
}
static inline u32 gr_gpcs_pri_mmu_ctrl_atomic_capability_sys_ncoh_mode_m(void)
{
return U32(0x1U) << 27U;
}
static inline u32 gr_gpcs_pri_mmu_pm_unit_mask_r(void)
{
return 0x00418890U;