mirror of
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gpu: nvgpu: add support for disabling l3 via DT
On volta the GPU determines whether to do L3 allocation for a mapping by
checking bit 36 of the physical address. So if a mapping should allocate lines
in the L3 this bit must be set.
However, when the physical addresses for 64GB of RAM uses the 36th bit
resulting in a conflict. Thus, add support for disabling l3 support
for SKUs having 64GB of physical memory.
Bug 3486025
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Change-Id: Ic540e754274cf1d9e6625493962699d21509e540
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2661548
(cherry picked from commit 46b43d2b24)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2668255
Reviewed-by: Brad Griffis <bgriffis@nvidia.com>
Reviewed-by: Amulya Yarlagadda <ayarlagadda@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Brad Griffis <bgriffis@nvidia.com>
This commit is contained in:
committed by
Amulya Yarlagadda
parent
7bf2833f34
commit
25bddffbfa
@@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2017-2022, NVIDIA CORPORATION. All rights reserved.
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*
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* copy of this software and associated documentation files (the "Software"),
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@@ -85,7 +85,12 @@ struct gk20a;
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#define NVGPU_MM_USE_PHYSICAL_SG 27
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#define NVGPU_MM_USE_PHYSICAL_SG 27
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/* WAR for gm20b chips. */
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/* WAR for gm20b chips. */
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#define NVGPU_MM_FORCE_128K_PMU_VM 28
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#define NVGPU_MM_FORCE_128K_PMU_VM 28
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/* SW ERRATA to disable L3 alloc Bit of the physical address.
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* Bit number varies between SOCs.
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* E.g. 64GB physical RAM support for gv11b requires this SW errata
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* to be enabled.
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*/
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#define NVGPU_DISABLE_L3_SUPPORT 29
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/*
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/*
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* Host flags
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* Host flags
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*/
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*/
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@@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved.
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*
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*
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* This program is free software; you can redistribute it and/or modify it
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* under the terms and conditions of the GNU General Public License,
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@@ -18,6 +18,7 @@
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#include <linux/dma-mapping.h>
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#include <linux/dma-mapping.h>
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#include <linux/mm.h>
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#include <linux/mm.h>
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#include <linux/slab.h>
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#include <linux/slab.h>
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#include <linux/of_platform.h>
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#include <uapi/linux/nvgpu.h>
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#include <uapi/linux/nvgpu.h>
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#include <nvgpu/defaults.h>
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#include <nvgpu/defaults.h>
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@@ -241,6 +242,8 @@ int nvgpu_probe(struct gk20a *g,
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struct device *dev = dev_from_gk20a(g);
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struct device *dev = dev_from_gk20a(g);
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struct gk20a_platform *platform = dev_get_drvdata(dev);
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struct gk20a_platform *platform = dev_get_drvdata(dev);
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int err = 0;
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int err = 0;
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struct device_node *np = dev->of_node;
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bool disable_l3_alloc = false;
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nvgpu_init_vars(g);
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nvgpu_init_vars(g);
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nvgpu_init_gr_vars(g);
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nvgpu_init_gr_vars(g);
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@@ -265,6 +268,12 @@ int nvgpu_probe(struct gk20a *g,
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return err;
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return err;
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}
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}
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disable_l3_alloc = of_property_read_bool(np, "disable_l3_alloc");
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if (disable_l3_alloc) {
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nvgpu_log_info(g, "L3 alloc is disabled\n");
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__nvgpu_set_enabled(g, NVGPU_DISABLE_L3_SUPPORT, true);
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}
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nvgpu_init_mm_vars(g);
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nvgpu_init_mm_vars(g);
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/* platform probe can defer do user init only if probe succeeds */
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/* platform probe can defer do user init only if probe succeeds */
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@@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2017-2022, NVIDIA CORPORATION. All rights reserved.
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*
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*
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* This program is free software; you can redistribute it and/or modify it
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* under the terms and conditions of the GNU General Public License,
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@@ -50,8 +50,10 @@ static u32 nvgpu_vm_translate_linux_flags(struct gk20a *g, u32 flags)
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core_flags |= NVGPU_VM_MAP_IO_COHERENT;
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core_flags |= NVGPU_VM_MAP_IO_COHERENT;
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if (flags & NVGPU_AS_MAP_BUFFER_FLAGS_UNMAPPED_PTE)
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if (flags & NVGPU_AS_MAP_BUFFER_FLAGS_UNMAPPED_PTE)
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core_flags |= NVGPU_VM_MAP_UNMAPPED_PTE;
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core_flags |= NVGPU_VM_MAP_UNMAPPED_PTE;
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if (flags & NVGPU_AS_MAP_BUFFER_FLAGS_L3_ALLOC)
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if (!nvgpu_is_enabled(g, NVGPU_DISABLE_L3_SUPPORT)) {
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core_flags |= NVGPU_VM_MAP_L3_ALLOC;
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if (flags & NVGPU_AS_MAP_BUFFER_FLAGS_L3_ALLOC)
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core_flags |= NVGPU_VM_MAP_L3_ALLOC;
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}
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if (flags & NVGPU_AS_MAP_BUFFER_FLAGS_DIRECT_KIND_CTRL)
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if (flags & NVGPU_AS_MAP_BUFFER_FLAGS_DIRECT_KIND_CTRL)
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core_flags |= NVGPU_VM_MAP_DIRECT_KIND_CTRL;
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core_flags |= NVGPU_VM_MAP_DIRECT_KIND_CTRL;
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if (flags & NVGPU_AS_MAP_BUFFER_FLAGS_PLATFORM_ATOMIC)
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if (flags & NVGPU_AS_MAP_BUFFER_FLAGS_PLATFORM_ATOMIC)
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@@ -1,7 +1,7 @@
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/*
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/*
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* Virtualized GPU Memory Management
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* Virtualized GPU Memory Management
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*
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*
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* Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2015-2022, NVIDIA CORPORATION. All rights reserved.
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*
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* copy of this software and associated documentation files (the "Software"),
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@@ -177,8 +177,10 @@ u64 vgpu_gp10b_locked_gmmu_map(struct vm_gk20a *vm,
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p->flags = TEGRA_VGPU_MAP_CACHEABLE;
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p->flags = TEGRA_VGPU_MAP_CACHEABLE;
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if (flags & NVGPU_VM_MAP_IO_COHERENT)
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if (flags & NVGPU_VM_MAP_IO_COHERENT)
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p->flags |= TEGRA_VGPU_MAP_IO_COHERENT;
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p->flags |= TEGRA_VGPU_MAP_IO_COHERENT;
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if (flags & NVGPU_VM_MAP_L3_ALLOC)
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if (!nvgpu_is_enabled(g, NVGPU_DISABLE_L3_SUPPORT)) {
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p->flags |= TEGRA_VGPU_MAP_L3_ALLOC;
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if (flags & NVGPU_VM_MAP_L3_ALLOC)
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p->flags |= TEGRA_VGPU_MAP_L3_ALLOC;
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}
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if (flags & NVGPU_VM_MAP_PLATFORM_ATOMIC) {
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if (flags & NVGPU_VM_MAP_PLATFORM_ATOMIC) {
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p->flags |= TEGRA_VGPU_MAP_PLATFORM_ATOMIC;
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p->flags |= TEGRA_VGPU_MAP_PLATFORM_ATOMIC;
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}
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}
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