diff --git a/drivers/gpu/nvgpu/common/nvlink/nvlink.c b/drivers/gpu/nvgpu/common/nvlink/nvlink.c
index 882f797bc..a81ea8034 100644
--- a/drivers/gpu/nvgpu/common/nvlink/nvlink.c
+++ b/drivers/gpu/nvgpu/common/nvlink/nvlink.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -27,11 +27,6 @@
 
 #ifdef CONFIG_NVGPU_NVLINK
 
-int nvgpu_nvlink_speed_config(struct gk20a *g)
-{
-	return g->ops.nvlink.speed_config(g);
-}
-
 int nvgpu_nvlink_early_init(struct gk20a *g)
 {
 	return g->ops.nvlink.early_init(g);
diff --git a/drivers/gpu/nvgpu/common/nvlink/nvlink_gv100.c b/drivers/gpu/nvgpu/common/nvlink/nvlink_gv100.c
index c00315011..67f07031c 100644
--- a/drivers/gpu/nvgpu/common/nvlink/nvlink_gv100.c
+++ b/drivers/gpu/nvgpu/common/nvlink/nvlink_gv100.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -822,12 +822,6 @@ int gv100_nvlink_early_init(struct gk20a *g)
 		return -EINVAL;
 	}
 
-	err = nvgpu_bios_get_lpwr_nvlink_table_hdr(g);
-	if (err != 0) {
-		nvgpu_err(g, "Failed to read LWPR_NVLINK_TABLE header\n");
-		goto exit;
-	}
-
 	err = nvgpu_bios_get_nvlink_config_data(g);
 	if (err != 0) {
 		nvgpu_err(g, "failed to read nvlink vbios data");
@@ -892,6 +886,7 @@ int gv100_nvlink_early_init(struct gk20a *g)
 		goto nvlink_init_exit;
 	}
 
+	g->nvlink.speed = nvgpu_nvlink_speed_20G;
 	err = gv100_nvlink_state_load_hal(g);
 	if (err != 0) {
 		nvgpu_err(g, " failed Nvlink state load");
@@ -913,12 +908,4 @@ exit:
 	return err;
 }
 
-int gv100_nvlink_speed_config(struct gk20a *g)
-{
-	g->nvlink.speed = nvgpu_nvlink_speed_20G;
-	g->nvlink.initpll_ordinal = INITPLL_1;
-	g->nvlink.initpll_cmd = NVGPU_NVLINK_MINION_DLCMD_INITPLL_1;
-	return 0;
-}
-
 #endif /* CONFIG_NVGPU_NVLINK */
diff --git a/drivers/gpu/nvgpu/common/nvlink/nvlink_gv100.h b/drivers/gpu/nvgpu/common/nvlink/nvlink_gv100.h
index ba8b5f7f3..c8e7bbf46 100644
--- a/drivers/gpu/nvgpu/common/nvlink/nvlink_gv100.h
+++ b/drivers/gpu/nvgpu/common/nvlink/nvlink_gv100.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -39,5 +39,4 @@ int gv100_nvlink_interface_init(struct gk20a *g);
 int gv100_nvlink_interface_disable(struct gk20a *g);
 int gv100_nvlink_shutdown(struct gk20a *g);
 int gv100_nvlink_early_init(struct gk20a *g);
-int gv100_nvlink_speed_config(struct gk20a *g);
 #endif
diff --git a/drivers/gpu/nvgpu/common/nvlink/nvlink_tu104.c b/drivers/gpu/nvgpu/common/nvlink/nvlink_tu104.c
index 8304e1cdc..72dde0b65 100644
--- a/drivers/gpu/nvgpu/common/nvlink/nvlink_tu104.c
+++ b/drivers/gpu/nvgpu/common/nvlink/nvlink_tu104.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -29,7 +29,6 @@
 #include <nvgpu/io.h>
 #include <nvgpu/timers.h>
 #include <nvgpu/gk20a.h>
-#include <nvgpu/nvlink_bios.h>
 #include <nvgpu/nvlink_minion.h>
 
 #include "nvlink_gv100.h"
@@ -93,33 +92,4 @@ void tu104_nvlink_get_connected_link_mask(u32 *link_mask)
 	*link_mask = TU104_CONNECTED_LINK_MASK;
 }
 
-int tu104_nvlink_speed_config(struct gk20a *g)
-{
-	int ret = 0;
-
-	ret = nvgpu_bios_get_lpwr_nvlink_table_hdr(g);
-	if (ret != 0) {
-		nvgpu_err(g, "Failed to read LWPR_NVLINK_TABLE header\n");
-		return ret;
-	}
-
-	switch (g->nvlink.initpll_ordinal) {
-	case INITPLL_1:
-		g->nvlink.speed = nvgpu_nvlink_speed_20G;
-		g->nvlink.initpll_cmd = NVGPU_NVLINK_MINION_DLCMD_INITPLL_1;
-		break;
-	case INITPLL_7:
-		g->nvlink.speed = nvgpu_nvlink_speed_16G;
-		g->nvlink.initpll_cmd = NVGPU_NVLINK_MINION_DLCMD_INITPLL_7;
-		break;
-	default:
-		nvgpu_err(g, "Nvlink initpll %d from VBIOS not supported.",
-					g->nvlink.initpll_ordinal);
-		ret = -EINVAL;
-		break;
-	}
-
-	return ret;
-}
-
 #endif /* CONFIG_NVGPU_NVLINK */
diff --git a/drivers/gpu/nvgpu/common/nvlink/nvlink_tu104.h b/drivers/gpu/nvgpu/common/nvlink/nvlink_tu104.h
index 8002315e9..afa3a20b5 100644
--- a/drivers/gpu/nvgpu/common/nvlink/nvlink_tu104.h
+++ b/drivers/gpu/nvgpu/common/nvlink/nvlink_tu104.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -30,5 +30,4 @@ struct gk20a;
 /* API */
 int tu104_nvlink_rxdet(struct gk20a *g, u32 link_id);
 void tu104_nvlink_get_connected_link_mask(u32 *link_mask);
-int tu104_nvlink_speed_config(struct gk20a *g);
 #endif
diff --git a/drivers/gpu/nvgpu/common/vbios/nvlink_bios.c b/drivers/gpu/nvgpu/common/vbios/nvlink_bios.c
index 2a3a5c844..b2588a5fb 100644
--- a/drivers/gpu/nvgpu/common/vbios/nvlink_bios.c
+++ b/drivers/gpu/nvgpu/common/vbios/nvlink_bios.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2015-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -71,35 +71,3 @@ int nvgpu_bios_get_nvlink_config_data(struct gk20a *g)
 
 	return ret;
 }
-
-int nvgpu_bios_get_lpwr_nvlink_table_hdr(struct gk20a *g)
-{
-	struct lpwr_nvlink_table_hdr_v1 hdr;
-	u8 *lpwr_nvlink_tbl_hdr_ptr = NULL;
-
-	lpwr_nvlink_tbl_hdr_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
-					nvgpu_bios_get_bit_token(g,
-						NVGPU_BIOS_PERF_TOKEN),
-					LPWR_NVLINK_TABLE);
-	if (lpwr_nvlink_tbl_hdr_ptr == NULL) {
-		nvgpu_err(g, "Invalid pointer to LPWR_NVLINK_TABLE\n");
-		return -EINVAL;
-	}
-
-	nvgpu_memcpy((u8 *)&hdr, lpwr_nvlink_tbl_hdr_ptr,
-			LPWR_NVLINK_TABLE_10_HDR_SIZE_06);
-
-	if (hdr.version != LWPR_NVLINK_TABLE_10_HDR_VER_10) {
-		nvgpu_err(g, "Unsupported LPWR_NVLINK_TABLE version: 0x%x",
-				hdr.version);
-		return -EINVAL;
-	}
-
-	g->nvlink.initpll_ordinal =
-		BIOS_GET_FIELD(u8, hdr.line_rate_initpll_ordinal,
-			VBIOS_LPWR_NVLINK_TABLE_HDR_INITPLL_ORDINAL);
-	nvgpu_log(g, gpu_dbg_nvlink, " Nvlink initpll_ordinal: 0x%x",
-				g->nvlink.initpll_ordinal);
-
-	return 0;
-}
diff --git a/drivers/gpu/nvgpu/hal/init/hal_tu104.c b/drivers/gpu/nvgpu/hal/init/hal_tu104.c
index e12561db2..36a62b809 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_tu104.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_tu104.c
@@ -1489,7 +1489,6 @@ static const struct gpu_ops tu104_ops = {
 		.reg_init = gv100_nvlink_reg_init,
 		.shutdown = gv100_nvlink_shutdown,
 		.early_init = gv100_nvlink_early_init,
-		.speed_config = tu104_nvlink_speed_config,
 		.minion = {
 			.base_addr = gv100_nvlink_minion_base_addr,
 			.is_running = gv100_nvlink_minion_is_running,
diff --git a/drivers/gpu/nvgpu/hal/nvlink/link_mode_transitions_gv100.c b/drivers/gpu/nvgpu/hal/nvlink/link_mode_transitions_gv100.c
index 10bc58e7d..f489c1d22 100644
--- a/drivers/gpu/nvgpu/hal/nvlink/link_mode_transitions_gv100.c
+++ b/drivers/gpu/nvgpu/hal/nvlink/link_mode_transitions_gv100.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -40,6 +40,7 @@ static int gv100_nvlink_init_uphy(struct gk20a *g, unsigned long mask,
 					bool sync)
 {
 	int err = 0;
+	enum nvgpu_nvlink_minion_dlcmd init_pll_cmd;
 	u32 link_id, master_pll, slave_pll;
 	u32 master_state, slave_state;
 	u32 link_enable;
@@ -47,6 +48,13 @@ static int gv100_nvlink_init_uphy(struct gk20a *g, unsigned long mask,
 
 	link_enable = g->ops.nvlink.get_link_reset_mask(g);
 
+	if ((g->nvlink.speed) == nvgpu_nvlink_speed_20G) {
+		init_pll_cmd = NVGPU_NVLINK_MINION_DLCMD_INITPLL_1;
+	} else {
+		nvgpu_err(g, "Unsupported UPHY speed");
+		return -EINVAL;
+	}
+
 	for_each_set_bit(bit, &mask, NVLINK_MAX_LINKS_SW) {
 		link_id = (u32)bit;
 		master_pll = g->nvlink.links[link_id].pll_master_link_id;
@@ -77,7 +85,7 @@ static int gv100_nvlink_init_uphy(struct gk20a *g, unsigned long mask,
 		/* Check if INIT PLL is done on link */
 		if ((BIT(master_pll) & g->nvlink.init_pll_done) == 0U) {
 			err = g->ops.nvlink.minion.send_dlcmd(g, master_pll,
-						g->nvlink.initpll_cmd, sync);
+						init_pll_cmd, sync);
 			if (err != 0) {
 				nvgpu_err(g, " Error sending INITPLL to minion");
 				return err;
diff --git a/drivers/gpu/nvgpu/hal/nvlink/minion_gv100.c b/drivers/gpu/nvgpu/hal/nvlink/minion_gv100.c
index 2721b68dd..7b8841108 100644
--- a/drivers/gpu/nvgpu/hal/nvlink/minion_gv100.c
+++ b/drivers/gpu/nvgpu/hal/nvlink/minion_gv100.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -175,9 +175,6 @@ u32 gv100_nvlink_minion_get_dlcmd_ordinal(struct gk20a *g,
 	case NVGPU_NVLINK_MINION_DLCMD_INITPLL_1:
 		dlcmd_ordinal = minion_nvlink_dl_cmd_command_initpll_1_v();
 		break;
-	case NVGPU_NVLINK_MINION_DLCMD_INITPLL_7:
-		dlcmd_ordinal = minion_nvlink_dl_cmd_command_initpll_7_v();
-		break;
 	default:
 		dlcmd_ordinal = U32_MAX;
 		break;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/bios.h b/drivers/gpu/nvgpu/include/nvgpu/bios.h
index 081208839..69c82b4be 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/bios.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/bios.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -65,7 +65,6 @@ enum {
 	LOWPOWER_TABLE,
 	LOWPOWER_GR_TABLE = 32,
 	LOWPOWER_MS_TABLE = 33,
-	LPWR_NVLINK_TABLE = 39,
 };
 
 enum {
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
index 10ee7b186..129cbc43f 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
@@ -547,7 +547,6 @@ struct gpu_ops {
 		int (*reg_init)(struct gk20a *g);
 		int (*shutdown)(struct gk20a *g);
 		int (*early_init)(struct gk20a *g);
-		int (*speed_config)(struct gk20a *g);
 		struct {
 			u32 (*base_addr)(struct gk20a *g);
 			bool (*is_running)(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvlink.h b/drivers/gpu/nvgpu/include/nvgpu/nvlink.h
index 1a4b08231..bf6e3b99e 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/nvlink.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/nvlink.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -31,9 +31,6 @@
 #define NV_NVLINK_REG_POLL_TIMEOUT_MS           3000
 #define NV_NVLINK_TIMEOUT_DELAY_US              5
 
-#define INITPLL_1				U8(1)
-#define INITPLL_7				U8(7)
-
 #define IOCTRL_REG_RD32(g, off) gk20a_readl(g, (g)->nvlink.ioctrl_base + (off))
 #define IOCTRL_REG_WR32(g, off, v) gk20a_writel(g, (g)->nvlink.ioctrl_base + (off), (v))
 #define MIF_REG_RD32(g, id, off) gk20a_readl(g, (g)->nvlink.links[(id)].mif_base + (off))
@@ -109,7 +106,6 @@ struct nvgpu_nvlink_link {
 
 
 enum nvgpu_nvlink_speed {
-	nvgpu_nvlink_speed_16G = 16,
 	nvgpu_nvlink_speed_20G = 20,
 	nvgpu_nvlink_speed__last,
 };
@@ -163,7 +159,6 @@ struct nvgpu_nvlink_dev {
 	u32 link_refclk_mask;
 	u8 train_at_boot;
 	u32 ac_coupling_mask;
-	u8 initpll_ordinal;
 
 	u32 connected_links;
 	u32 initialized_links;
@@ -171,7 +166,6 @@ struct nvgpu_nvlink_dev {
 	u32 init_pll_done;
 
 	enum nvgpu_nvlink_speed speed;
-	enum nvgpu_nvlink_minion_dlcmd initpll_cmd;
 
 	/* tlc cached errors */
 	u32 tlc_rx_err_status_0[NVLINK_MAX_LINKS_SW];
@@ -182,7 +176,6 @@ struct nvgpu_nvlink_dev {
 	void *priv;
 };
 
-int nvgpu_nvlink_speed_config(struct gk20a *g);
 int nvgpu_nvlink_early_init(struct gk20a *g);
 int nvgpu_nvlink_link_early_init(struct gk20a *g);
 int nvgpu_nvlink_interface_init(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvlink_bios.h b/drivers/gpu/nvgpu/include/nvgpu/nvlink_bios.h
index af8208d42..81171de00 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/nvlink_bios.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/nvlink_bios.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -42,21 +42,8 @@ struct nvlink_config_data_hdr_v1 {
 	u32 ac_coupling_mask;
 } __attribute__((packed));
 
-#define LWPR_NVLINK_TABLE_10_HDR_VER_10         0x10U
-#define LPWR_NVLINK_TABLE_10_HDR_SIZE_06        6U
-
-struct lpwr_nvlink_table_hdr_v1 {
-	u8 version;
-	u8 hdr_size;
-	u8 entry_size;
-	u8 entry_count;
-	u8 default_entry_idx;
-	u8 line_rate_initpll_ordinal;
-} __attribute__((packed));
-
 struct gk20a;
 
 int nvgpu_bios_get_nvlink_config_data(struct gk20a *g);
-int nvgpu_bios_get_lpwr_nvlink_table_hdr(struct gk20a *g);
 
 #endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvlink_minion.h b/drivers/gpu/nvgpu/include/nvgpu/nvlink_minion.h
index dfc8d10d1..a322347e1 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/nvlink_minion.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/nvlink_minion.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -42,7 +42,6 @@ enum nvgpu_nvlink_minion_dlcmd {
 	NVGPU_NVLINK_MINION_DLCMD_LANESHUTDOWN,
 	NVGPU_NVLINK_MINION_DLCMD_TXCLKSWITCH_PLL,
 	NVGPU_NVLINK_MINION_DLCMD_INITPLL_1,
-	NVGPU_NVLINK_MINION_DLCMD_INITPLL_7,
 	NVGPU_NVLINK_MINION_DLCMD_TURING_INITDLPL_TO_CHIPA,
 	NVGPU_NVLINK_MINION_DLCMD_TURING_RXDET,
 	NVGPU_NVLINK_MINION_DLCMD__LAST,
diff --git a/drivers/gpu/nvgpu/os/linux/nvlink_probe.c b/drivers/gpu/nvgpu/os/linux/nvlink_probe.c
index dee776e15..b99c44de8 100644
--- a/drivers/gpu/nvgpu/os/linux/nvlink_probe.c
+++ b/drivers/gpu/nvgpu/os/linux/nvlink_probe.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -77,23 +77,6 @@ fail:
 	return -ENODEV;
 }
 
-static int nvgpu_nvlink_ops_speed_config(struct nvlink_device *ndev)
-{
-	struct gk20a *g = (struct gk20a *) ndev->priv;
-	int err;
-
-	err = nvgpu_nvlink_speed_config(g);
-	if (err != 0) {
-		nvgpu_err(g, "Nvlink speed config failed.\n");
-	} else {
-		ndev->speed = g->nvlink.speed;
-		nvgpu_log(g, gpu_dbg_nvlink, "Nvlink default speed set to %d\n",
-					ndev->speed);
-	}
-
-	return err;
-}
-
 static int nvgpu_nvlink_ops_early_init(struct nvlink_device *ndev)
 {
 	struct gk20a *g = (struct gk20a *) ndev->priv;
@@ -413,7 +396,6 @@ int nvgpu_nvlink_init_ops(struct gk20a *g)
 	ndev->dev_ops.dev_interface_disable =
 					nvgpu_nvlink_ops_interface_disable;
 	ndev->dev_ops.dev_shutdown = nvgpu_nvlink_ops_dev_shutdown;
-	ndev->dev_ops.dev_speed_config = nvgpu_nvlink_ops_speed_config;
 
 	/* Fill in the link struct */
 	ndev->link.device_id = ndev->device_id;