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gpu: nvgpu: move clk_gm20b debugfs to Linux module
Move debugfs code from clk_gm20b.c to file in Linux module common/linux/debug_clk.c This file will be compiled only if CONFIG_DEBUG_FS is set Define below new HAL APIs for various clock operations which can be accessed from debug file init_debugfs() get_voltage() get_gpcclk_clock_counter() pll_reg_write() get_pll_debug_data() Export nvgpu_pl_to_div() and nvgpu_div_to_pl() so that these can be accessed from debug_clk.c Add new structure nvgpu_clk_pll_debug_data so that all required register values for debugging can be made available in debug_clk.c Add new API gm20b_get_gpc_pll_parms() so that statically defined variable can be accessed in debug_clk.c too Remove global variable dvfs_safe_max_freq and add it to struct clk_gk20a so that it can accessed from both clk_gm20b.c and debug_clk.c Jira NVGPU-62 Change-Id: I3ae70b40235e78141a686686930e1f178ad59453 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1488903 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
Deepak Nibade
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9902a49b0b
commit
26487b82df
271
drivers/gpu/nvgpu/common/linux/debug_clk.c
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271
drivers/gpu/nvgpu/common/linux/debug_clk.c
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@@ -0,0 +1,271 @@
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/*
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* Copyright (C) 2017 NVIDIA Corporation. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/uaccess.h>
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#include <linux/debugfs.h>
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#include <linux/seq_file.h>
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#include "gk20a/platform_gk20a.h"
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#include "gm20b/clk_gm20b.h"
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static int rate_get(void *data, u64 *val)
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{
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struct gk20a *g = (struct gk20a *)data;
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struct clk_gk20a *clk = &g->clk;
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*val = (u64)rate_gpc2clk_to_gpu(clk->gpc_pll.freq);
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return 0;
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}
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static int rate_set(void *data, u64 val)
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{
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struct gk20a *g = (struct gk20a *)data;
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return g->ops.clk.set_rate(g, CTRL_CLK_DOMAIN_GPCCLK, (u32)val);
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}
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DEFINE_SIMPLE_ATTRIBUTE(rate_fops, rate_get, rate_set, "%llu\n");
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static int pll_reg_show(struct seq_file *s, void *data)
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{
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struct gk20a *g = s->private;
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struct nvgpu_clk_pll_debug_data d;
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u32 reg, m, n, pl, f;
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int err = 0;
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if (g->ops.clk.get_pll_debug_data) {
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err = g->ops.clk.get_pll_debug_data(g, &d);
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if (err)
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return err;
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} else {
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return -EINVAL;
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}
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seq_printf(s, "bypassctrl = %s, ",
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d.trim_sys_bypassctrl_val ? "bypass" : "vco");
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seq_printf(s, "sel_vco = %s, ",
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d.trim_sys_sel_vco_val ? "vco" : "bypass");
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seq_printf(s, "cfg = 0x%x : %s : %s : %s\n", d.trim_sys_gpcpll_cfg_val,
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d.trim_sys_gpcpll_cfg_enabled ? "enabled" : "disabled",
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d.trim_sys_gpcpll_cfg_locked ? "locked" : "unlocked",
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d.trim_sys_gpcpll_cfg_sync_on ? "sync_on" : "sync_off");
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reg = d.trim_sys_gpcpll_coeff_val;
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m = d.trim_sys_gpcpll_coeff_mdiv;
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n = d.trim_sys_gpcpll_coeff_ndiv;
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pl = d.trim_sys_gpcpll_coeff_pldiv;
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f = g->clk.gpc_pll.clk_in * n / (m * nvgpu_pl_to_div(pl));
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seq_printf(s, "coef = 0x%x : m = %u : n = %u : pl = %u", reg, m, n, pl);
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seq_printf(s, " : pll_f(gpu_f) = %u(%u) kHz\n", f, f/2);
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seq_printf(s, "dvfs0 = 0x%x : d = %u : dmax = %u : doffs = %u\n",
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d.trim_sys_gpcpll_dvfs0_val,
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d.trim_sys_gpcpll_dvfs0_dfs_coeff,
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d.trim_sys_gpcpll_dvfs0_dfs_det_max,
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d.trim_sys_gpcpll_dvfs0_dfs_dc_offset);
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return 0;
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}
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static int pll_reg_open(struct inode *inode, struct file *file)
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{
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return single_open(file, pll_reg_show, inode->i_private);
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}
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static const struct file_operations pll_reg_fops = {
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.open = pll_reg_open,
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.read = seq_read,
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.llseek = seq_lseek,
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.release = single_release,
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};
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static int pll_reg_raw_show(struct seq_file *s, void *data)
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{
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struct gk20a *g = s->private;
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struct nvgpu_clk_pll_debug_data d;
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u32 reg;
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int err = 0;
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if (g->ops.clk.get_pll_debug_data) {
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err = g->ops.clk.get_pll_debug_data(g, &d);
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if (err)
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return err;
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} else {
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return -EINVAL;
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}
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seq_puts(s, "GPCPLL REGISTERS:\n");
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for (reg = d.trim_sys_gpcpll_cfg_reg;
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reg <= d.trim_sys_gpcpll_dvfs2_reg;
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reg += sizeof(u32))
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seq_printf(s, "[0x%02x] = 0x%08x\n", reg, gk20a_readl(g, reg));
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seq_puts(s, "\nGPC CLK OUT REGISTERS:\n");
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seq_printf(s, "[0x%02x] = 0x%08x\n", d.trim_sys_sel_vco_reg,
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d.trim_sys_sel_vco_val);
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seq_printf(s, "[0x%02x] = 0x%08x\n", d.trim_sys_gpc2clk_out_reg,
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d.trim_sys_gpc2clk_out_val);
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seq_printf(s, "[0x%02x] = 0x%08x\n", d.trim_sys_bypassctrl_reg,
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d.trim_sys_bypassctrl_val);
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return 0;
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}
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static int pll_reg_raw_open(struct inode *inode, struct file *file)
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{
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return single_open(file, pll_reg_raw_show, inode->i_private);
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}
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static ssize_t pll_reg_raw_write(struct file *file,
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const char __user *userbuf, size_t count, loff_t *ppos)
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{
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struct gk20a *g = file->f_path.dentry->d_inode->i_private;
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char buf[80];
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u32 reg, val;
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int err = 0;
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if (sizeof(buf) <= count)
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return -EINVAL;
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if (copy_from_user(buf, userbuf, count))
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return -EFAULT;
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/* terminate buffer and trim - white spaces may be appended
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* at the end when invoked from shell command line */
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buf[count] = '\0';
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strim(buf);
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if (sscanf(buf, "[0x%x] = 0x%x", ®, &val) != 2)
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return -EINVAL;
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if (g->ops.clk.pll_reg_write(g, reg, val))
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err = g->ops.clk.pll_reg_write(g, reg, val);
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else
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err = -EINVAL;
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return err;
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}
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static const struct file_operations pll_reg_raw_fops = {
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.open = pll_reg_raw_open,
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.read = seq_read,
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.write = pll_reg_raw_write,
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.llseek = seq_lseek,
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.release = single_release,
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};
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static int monitor_get(void *data, u64 *val)
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{
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struct gk20a *g = (struct gk20a *)data;
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int err = 0;
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if (g->ops.clk.get_gpcclk_clock_counter)
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err = g->ops.clk.get_gpcclk_clock_counter(&g->clk, val);
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else
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err = -EINVAL;
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return err;
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}
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DEFINE_SIMPLE_ATTRIBUTE(monitor_fops, monitor_get, NULL, "%llu\n");
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static int voltage_get(void *data, u64 *val)
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{
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struct gk20a *g = (struct gk20a *)data;
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int err = 0;
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if (g->ops.clk.get_voltage)
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err = g->ops.clk.get_voltage(&g->clk, val);
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else
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err = -EINVAL;
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return err;
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}
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DEFINE_SIMPLE_ATTRIBUTE(voltage_fops, voltage_get, NULL, "%llu\n");
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static int pll_param_show(struct seq_file *s, void *data)
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{
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struct pll_parms *gpc_pll_params = gm20b_get_gpc_pll_parms();
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seq_printf(s, "ADC offs = %d uV, ADC slope = %d uV, VCO ctrl = 0x%x\n",
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gpc_pll_params->uvdet_offs, gpc_pll_params->uvdet_slope,
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gpc_pll_params->vco_ctrl);
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return 0;
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}
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static int pll_param_open(struct inode *inode, struct file *file)
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{
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return single_open(file, pll_param_show, inode->i_private);
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}
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static const struct file_operations pll_param_fops = {
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.open = pll_param_open,
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.read = seq_read,
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.llseek = seq_lseek,
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.release = single_release,
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};
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int gm20b_clk_init_debugfs(struct gk20a *g)
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{
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struct dentry *d;
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struct gk20a_platform *platform = dev_get_drvdata(g->dev);
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if (!platform->debugfs)
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return -EINVAL;
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d = debugfs_create_file(
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"rate", S_IRUGO|S_IWUSR, platform->debugfs, g, &rate_fops);
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if (!d)
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goto err_out;
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d = debugfs_create_file(
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"pll_reg", S_IRUGO, platform->debugfs, g, &pll_reg_fops);
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if (!d)
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goto err_out;
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d = debugfs_create_file("pll_reg_raw",
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S_IRUGO, platform->debugfs, g, &pll_reg_raw_fops);
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if (!d)
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goto err_out;
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d = debugfs_create_file(
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"monitor", S_IRUGO, platform->debugfs, g, &monitor_fops);
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if (!d)
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goto err_out;
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d = debugfs_create_file(
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"voltage", S_IRUGO, platform->debugfs, g, &voltage_fops);
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if (!d)
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goto err_out;
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d = debugfs_create_file(
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"pll_param", S_IRUGO, platform->debugfs, g, &pll_param_fops);
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if (!d)
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goto err_out;
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d = debugfs_create_u32("pll_na_mode", S_IRUGO, platform->debugfs,
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(u32 *)&g->clk.gpc_pll.mode);
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if (!d)
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goto err_out;
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d = debugfs_create_u32("fmax2x_at_vmin_safe_t", S_IRUGO,
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platform->debugfs, (u32 *)&g->clk.dvfs_safe_max_freq);
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if (!d)
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goto err_out;
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return 0;
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err_out:
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pr_err("%s: Failed to make debugfs node\n", __func__);
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debugfs_remove_recursive(platform->debugfs);
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return -ENOMEM;
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}
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