From 2683ce089a094de43a26ff88f92343e5a3a72931 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Thu, 10 Jan 2019 15:31:26 -0800 Subject: [PATCH] gpu: nvgpu: Use Hw vals instead of CPU page size in sim Simulation used PAGE_SHIFT for values that are actually dependent on the fmodel implementation and not CPU page size. Fix that by introducing new HW constants. JIRA NVGPU-1734 Change-Id: Icaab8293ac9f6eeaae5d5424d55851cb53b365dd Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1992456 Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-misra GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/sim.c | 10 +++++----- drivers/gpu/nvgpu/common/sim_pci.c | 10 +++++----- drivers/gpu/nvgpu/include/nvgpu/hw_sim.h | 14 +++++++++++++- drivers/gpu/nvgpu/include/nvgpu/hw_sim_pci.h | 14 +++++++++++++- 4 files changed, 36 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/nvgpu/common/sim.c b/drivers/gpu/nvgpu/common/sim.c index b94afef6f..1f6f1935c 100644 --- a/drivers/gpu/nvgpu/common/sim.c +++ b/drivers/gpu/nvgpu/common/sim.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -119,7 +119,7 @@ static int rpc_send_message(struct gk20a *g) sim_dma_status_valid_f() | sim_dma_size_4kb_f() | sim_dma_addr_lo_f(nvgpu_mem_get_addr(g, &g->sim->msg_bfr) - >> PAGE_SHIFT); + >> sim_dma_addr_lo_b()); *sim_send_ring_bfr(g, dma_hi_offset*sizeof(u32)) = u64_hi32(nvgpu_mem_get_addr(g, &g->sim->msg_bfr)); @@ -168,7 +168,7 @@ static int rpc_recv_poll(struct gk20a *g) *sim_recv_ring_bfr(g, dma_hi_offset*4)); recv_phys_addr = (u64)recv_phys_addr_hi << 32 | - (u64)recv_phys_addr_lo << PAGE_SHIFT; + (u64)recv_phys_addr_lo << sim_dma_addr_lo_b(); if (recv_phys_addr != nvgpu_mem_get_addr(g, &g->sim->msg_bfr)) { @@ -265,7 +265,7 @@ static void nvgpu_sim_init_late(struct gk20a *g) sim_send_ring_status_valid_f() | sim_send_ring_target_phys_pci_coherent_f() | sim_send_ring_size_4kb_f() | - sim_send_ring_addr_lo_f(phys >> PAGE_SHIFT)); + sim_send_ring_addr_lo_f(phys >> sim_send_ring_addr_lo_b())); /*repeat for recv ring (but swap put,get as roles are opposite) */ sim_writel(g->sim, sim_recv_ring_r(), sim_recv_ring_status_invalid_f()); @@ -282,7 +282,7 @@ static void nvgpu_sim_init_late(struct gk20a *g) sim_recv_ring_status_valid_f() | sim_recv_ring_target_phys_pci_coherent_f() | sim_recv_ring_size_4kb_f() | - sim_recv_ring_addr_lo_f(phys >> PAGE_SHIFT)); + sim_recv_ring_addr_lo_f(phys >> sim_recv_ring_addr_lo_b())); return; } diff --git a/drivers/gpu/nvgpu/common/sim_pci.c b/drivers/gpu/nvgpu/common/sim_pci.c index 024a60d5b..c285b2096 100644 --- a/drivers/gpu/nvgpu/common/sim_pci.c +++ b/drivers/gpu/nvgpu/common/sim_pci.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -94,7 +94,7 @@ static int rpc_send_message(struct gk20a *g) sim_dma_status_valid_f() | sim_dma_size_4kb_f() | sim_dma_addr_lo_f(nvgpu_mem_get_phys_addr(g, &g->sim->msg_bfr) - >> PAGE_SHIFT); + >> sim_dma_addr_lo_b()); *sim_send_ring_bfr(g, dma_hi_offset*sizeof(u32)) = u64_hi32(nvgpu_mem_get_phys_addr(g, &g->sim->msg_bfr)); @@ -140,7 +140,7 @@ static int rpc_recv_poll(struct gk20a *g) *sim_recv_ring_bfr(g, dma_hi_offset*4)); recv_phys_addr = (u64)recv_phys_addr_hi << 32 | - (u64)recv_phys_addr_lo << PAGE_SHIFT; + (u64)recv_phys_addr_lo << sim_dma_addr_lo_b(); if (recv_phys_addr != nvgpu_mem_get_phys_addr(g, &g->sim->msg_bfr)) { @@ -234,7 +234,7 @@ static void nvgpu_sim_init_late(struct gk20a *g) sim_send_ring_status_valid_f() | sim_send_ring_target_phys_pci_coherent_f() | sim_send_ring_size_4kb_f() | - sim_send_ring_addr_lo_f(phys >> PAGE_SHIFT)); + sim_send_ring_addr_lo_f(phys >> sim_send_ring_addr_lo_b())); /* repeat for recv ring (but swap put,get as roles are opposite) */ sim_writel(g->sim, sim_recv_ring_r(), sim_recv_ring_status_invalid_f()); @@ -251,7 +251,7 @@ static void nvgpu_sim_init_late(struct gk20a *g) sim_recv_ring_status_valid_f() | sim_recv_ring_target_phys_pci_coherent_f() | sim_recv_ring_size_4kb_f() | - sim_recv_ring_addr_lo_f(phys >> PAGE_SHIFT)); + sim_recv_ring_addr_lo_f(phys >> sim_recv_ring_addr_lo_b())); } int nvgpu_init_sim_support_pci(struct gk20a *g) diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw_sim.h b/drivers/gpu/nvgpu/include/nvgpu/hw_sim.h index 89ce6da91..22c1a8a35 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw_sim.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw_sim.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2018, NVIDIA Corporation. + * Copyright (c) 2012-2019, NVIDIA Corporation. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -333,6 +333,10 @@ static inline u32 sim_send_ring_addr_lo__prod_f(void) { return 0x0; } +static inline u32 sim_send_ring_addr_lo_b(void) +{ + return 12U; +} static inline u32 sim_send_ring_hi_r(void) { return 0x00000004; @@ -685,6 +689,10 @@ static inline u32 sim_recv_ring_addr_lo__prod_f(void) { return 0x0; } +static inline u32 sim_recv_ring_addr_lo_b(void) +{ + return 12U; +} static inline u32 sim_recv_ring_hi_r(void) { return 0x00000014; @@ -2065,6 +2073,10 @@ static inline u32 sim_dma_addr_lo__prod_f(void) { return 0x0; } +static inline u32 sim_dma_addr_lo_b(void) +{ + return 12U; +} static inline u32 sim_dma_hi_r(void) { return 0x00000004; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw_sim_pci.h b/drivers/gpu/nvgpu/include/nvgpu/hw_sim_pci.h index 32dbeb4b0..4d46f0374 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw_sim_pci.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw_sim_pci.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2018, NVIDIA Corporation. + * Copyright (c) 2012-2019, NVIDIA Corporation. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -337,6 +337,10 @@ static inline u32 sim_send_ring_addr_lo__prod_f(void) { return 0x0U; } +static inline u32 sim_send_ring_addr_lo_b(void) +{ + return 12U; +} static inline u32 sim_send_ring_hi_r(void) { return 0x00000004U; @@ -689,6 +693,10 @@ static inline u32 sim_recv_ring_addr_lo__prod_f(void) { return 0x0U; } +static inline u32 sim_recv_ring_addr_lo_b(void) +{ + return 12U; +} static inline u32 sim_recv_ring_hi_r(void) { return 0x00000014U; @@ -2069,6 +2077,10 @@ static inline u32 sim_dma_addr_lo__prod_f(void) { return 0x0U; } +static inline u32 sim_dma_addr_lo_b(void) +{ + return 12U; +} static inline u32 sim_dma_hi_r(void) { return 0x00000004U;