diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 15070f467..d5b261a4e 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -234,6 +234,8 @@ nvgpu-y += \ hal/fifo/ramfc_gp10b.o \ hal/fifo/ramfc_gv11b.o \ hal/fifo/ramfc_tu104.o \ + hal/fifo/ramin_gk20a.o \ + hal/fifo/ramin_gv11b.o \ hal/fifo/tsg_gk20a.o \ hal/fifo/tsg_gv11b.o \ hal/fifo/userd_gk20a.o \ diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources index 4a8f970ae..7e9e00dda 100644 --- a/drivers/gpu/nvgpu/Makefile.sources +++ b/drivers/gpu/nvgpu/Makefile.sources @@ -366,6 +366,8 @@ srcs += common/sim.c \ hal/fifo/ramfc_gp10b.c \ hal/fifo/ramfc_gv11b.c \ hal/fifo/ramfc_tu104.c \ + hal/fifo/ramin_gk20a.c \ + hal/fifo/ramin_gv11b.c \ hal/fifo/tsg_gk20a.c \ hal/fifo/tsg_gv11b.c \ hal/fifo/userd_gk20a.c \ diff --git a/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c index b4ef04390..fb247b3a2 100644 --- a/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c @@ -500,6 +500,9 @@ static const struct gpu_ops vgpu_gp10b_ops = { .get_syncpt = NULL, .set_syncpt = NULL, }, + .ramin = { + .set_gr_ptr = NULL, + }, .runlist = { .reschedule = NULL, .update_for_channel = vgpu_runlist_update_for_channel, @@ -750,6 +753,7 @@ int vgpu_gp10b_init_hal(struct gk20a *g) gops->engine = vgpu_gp10b_ops.engine; gops->pbdma = vgpu_gp10b_ops.pbdma; gops->ramfc = vgpu_gp10b_ops.ramfc; + gops->ramin = vgpu_gp10b_ops.ramin; gops->runlist = vgpu_gp10b_ops.runlist; gops->userd = vgpu_gp10b_ops.userd; gops->channel = vgpu_gp10b_ops.channel; diff --git a/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c index 0d828f93a..8bb32b991 100644 --- a/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c @@ -589,6 +589,9 @@ static const struct gpu_ops vgpu_gv11b_ops = { .get_syncpt = NULL, .set_syncpt = NULL, }, + .ramin = { + .set_gr_ptr = NULL, + }, .runlist = { .reschedule = NULL, .update_for_channel = vgpu_runlist_update_for_channel, @@ -841,6 +844,7 @@ int vgpu_gv11b_init_hal(struct gk20a *g) gops->engine = vgpu_gv11b_ops.engine; gops->pbdma = vgpu_gv11b_ops.pbdma; gops->ramfc = vgpu_gv11b_ops.ramfc; + gops->ramin = vgpu_gv11b_ops.ramin; gops->runlist = vgpu_gv11b_ops.runlist; gops->userd = vgpu_gv11b_ops.userd; gops->channel = vgpu_gv11b_ops.channel; diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 6e748add0..4632069bf 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c @@ -181,21 +181,9 @@ static void gr_report_ctxsw_error(struct gk20a *g, u32 err_type, u32 chid, int gr_gk20a_commit_inst(struct channel_gk20a *c, u64 gpu_va) { - u32 addr_lo; - u32 addr_hi; - - nvgpu_log_fn(c->g, " "); - - addr_lo = u64_lo32(gpu_va) >> 12; - addr_hi = u64_hi32(gpu_va); - - nvgpu_mem_wr32(c->g, &c->inst_block, ram_in_gr_wfi_target_w(), - ram_in_gr_cs_wfi_f() | ram_in_gr_wfi_mode_virtual_f() | - ram_in_gr_wfi_ptr_lo_f(addr_lo)); - - nvgpu_mem_wr32(c->g, &c->inst_block, ram_in_gr_wfi_ptr_hi_w(), - ram_in_gr_wfi_ptr_hi_f(addr_hi)); + struct gk20a *g = c->g; + g->ops.ramin.set_gr_ptr(g, &c->inst_block, gpu_va); return 0; } diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index d64ab7a9c..18ad160af 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c @@ -58,6 +58,7 @@ #include "hal/fifo/engine_status_gm20b.h" #include "hal/fifo/pbdma_status_gm20b.h" #include "hal/fifo/ramfc_gk20a.h" +#include "hal/fifo/ramin_gk20a.h" #include "hal/fifo/tsg_gk20a.h" #include "hal/fifo/userd_gk20a.h" #include "hal/fifo/fifo_intr_gk20a.h" @@ -694,6 +695,9 @@ static const struct gpu_ops gm20b_ops = { .get_syncpt = NULL, .set_syncpt = NULL, }, + .ramin = { + .set_gr_ptr = gk20a_ramin_set_gr_ptr, + }, .runlist = { .update_for_channel = gk20a_runlist_update_for_channel, .reload = gk20a_runlist_reload, @@ -994,6 +998,7 @@ int gm20b_init_hal(struct gk20a *g) gops->engine = gm20b_ops.engine; gops->pbdma = gm20b_ops.pbdma; gops->ramfc = gm20b_ops.ramfc; + gops->ramin = gm20b_ops.ramin; gops->runlist = gm20b_ops.runlist; gops->userd = gm20b_ops.userd; gops->channel = gm20b_ops.channel; diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 24db6cc3e..1a52c3235 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -69,6 +69,7 @@ #include "hal/fifo/pbdma_status_gm20b.h" #include "hal/fifo/ramfc_gk20a.h" #include "hal/fifo/ramfc_gp10b.h" +#include "hal/fifo/ramin_gk20a.h" #include "hal/fifo/tsg_gk20a.h" #include "hal/fifo/userd_gk20a.h" #include "hal/fifo/fifo_intr_gk20a.h" @@ -781,6 +782,9 @@ static const struct gpu_ops gp10b_ops = { .get_syncpt = gp10b_ramfc_get_syncpt, .set_syncpt = gp10b_ramfc_set_syncpt, }, + .ramin = { + .set_gr_ptr = gk20a_ramin_set_gr_ptr, + }, .runlist = { .reschedule = gk20a_runlist_reschedule, .reschedule_preempt_next_locked = gk20a_fifo_reschedule_preempt_next, @@ -1090,6 +1094,7 @@ int gp10b_init_hal(struct gk20a *g) gops->engine = gp10b_ops.engine; gops->pbdma = gp10b_ops.pbdma; gops->ramfc = gp10b_ops.ramfc; + gops->ramin = gp10b_ops.ramin; gops->runlist = gp10b_ops.runlist; gops->userd = gp10b_ops.userd; gops->channel = gp10b_ops.channel; diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index d64acc236..a45cec0a1 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -58,6 +58,7 @@ #include "hal/fifo/pbdma_status_gm20b.h" #include "hal/fifo/ramfc_gp10b.h" #include "hal/fifo/ramfc_gv11b.h" +#include "hal/fifo/ramin_gv11b.h" #include "hal/fifo/tsg_gv11b.h" #include "hal/fifo/userd_gk20a.h" #include "hal/fifo/userd_gv11b.h" @@ -966,6 +967,9 @@ static const struct gpu_ops gv100_ops = { .get_syncpt = NULL, .set_syncpt = NULL, }, + .ramin = { + .set_gr_ptr = gv11b_ramin_set_gr_ptr, + }, .runlist = { .update_for_channel = gk20a_runlist_update_for_channel, .reload = gk20a_runlist_reload, @@ -1385,6 +1389,7 @@ int gv100_init_hal(struct gk20a *g) gops->engine = gv100_ops.engine; gops->pbdma = gv100_ops.pbdma; gops->ramfc = gv100_ops.ramfc; + gops->ramin = gv100_ops.ramin; gops->runlist = gv100_ops.runlist; gops->userd = gv100_ops.userd; gops->channel = gv100_ops.channel; diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 420989c9c..c11900acd 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -1962,8 +1962,6 @@ u32 gr_gv11b_get_nonpes_aware_tpc(struct gk20a *g, u32 gpc, u32 tpc) int gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va) { - u32 addr_lo; - u32 addr_hi; struct nvgpu_mem *ctxheader; struct gk20a *g = c->g; struct tsg_gk20a *tsg; @@ -1985,18 +1983,8 @@ int gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va) nvgpu_gr_subctx_load_ctx_header(g, c->subctx, tsg->gr_ctx, gpu_va); ctxheader = &c->subctx->ctx_header; - addr_lo = u64_lo32(ctxheader->gpu_va) >> ram_in_base_shift_v(); - addr_hi = u64_hi32(ctxheader->gpu_va); - - /* point this address to engine_wfi_ptr */ - nvgpu_mem_wr32(c->g, &c->inst_block, ram_in_engine_wfi_target_w(), - ram_in_engine_cs_wfi_v() | - ram_in_engine_wfi_mode_f(ram_in_engine_wfi_mode_virtual_v()) | - ram_in_engine_wfi_ptr_lo_f(addr_lo)); - - nvgpu_mem_wr32(c->g, &c->inst_block, ram_in_engine_wfi_ptr_hi_w(), - ram_in_engine_wfi_ptr_hi_f(addr_hi)); + g->ops.ramin.set_gr_ptr(g, &c->inst_block, ctxheader->gpu_va); return 0; } diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index fe109c8dc..6ad9f5f76 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -59,6 +59,7 @@ #include "hal/fifo/engines_gv11b.h" #include "hal/fifo/ramfc_gp10b.h" #include "hal/fifo/ramfc_gv11b.h" +#include "hal/fifo/ramin_gv11b.h" #include "hal/fifo/tsg_gv11b.h" #include "hal/fifo/userd_gk20a.h" #include "hal/fifo/userd_gv11b.h" @@ -921,6 +922,9 @@ static const struct gpu_ops gv11b_ops = { .get_syncpt = NULL, .set_syncpt = NULL, }, + .ramin = { + .set_gr_ptr = gv11b_ramin_set_gr_ptr, + }, .runlist = { .reschedule = gv11b_runlist_reschedule, .reschedule_preempt_next_locked = gk20a_fifo_reschedule_preempt_next, @@ -1255,6 +1259,7 @@ int gv11b_init_hal(struct gk20a *g) gops->engine = gv11b_ops.engine; gops->pbdma = gv11b_ops.pbdma; gops->ramfc = gv11b_ops.ramfc; + gops->ramin = gv11b_ops.ramin; gops->runlist = gv11b_ops.runlist; gops->userd = gv11b_ops.userd; gops->channel = gv11b_ops.channel; diff --git a/drivers/gpu/nvgpu/hal/fifo/ramin_gk20a.c b/drivers/gpu/nvgpu/hal/fifo/ramin_gk20a.c new file mode 100644 index 000000000..a4a678c8f --- /dev/null +++ b/drivers/gpu/nvgpu/hal/fifo/ramin_gk20a.c @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2011-2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include + +#include "hal/fifo/ramin_gk20a.h" + +#include + +void gk20a_ramin_set_gr_ptr(struct gk20a *g, + struct nvgpu_mem *inst_block, u64 gpu_va) +{ + u32 addr_lo = u64_lo32(gpu_va) >> ram_in_base_shift_v(); + u32 addr_hi = u64_hi32(gpu_va); + + nvgpu_mem_wr32(g, inst_block, ram_in_gr_wfi_target_w(), + ram_in_gr_cs_wfi_f() | ram_in_gr_wfi_mode_virtual_f() | + ram_in_gr_wfi_ptr_lo_f(addr_lo)); + + nvgpu_mem_wr32(g, inst_block, ram_in_gr_wfi_ptr_hi_w(), + ram_in_gr_wfi_ptr_hi_f(addr_hi)); +} diff --git a/drivers/gpu/nvgpu/hal/fifo/ramin_gk20a.h b/drivers/gpu/nvgpu/hal/fifo/ramin_gk20a.h new file mode 100644 index 000000000..5d50fadf8 --- /dev/null +++ b/drivers/gpu/nvgpu/hal/fifo/ramin_gk20a.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2011-2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef NVGPU_RAMIN_GK20A_H +#define NVGPU_RAMIN_GK20A_H + +#include + +struct gk20a; +struct nvgpu_mem; + +void gk20a_ramin_set_gr_ptr(struct gk20a *g, + struct nvgpu_mem *inst_block, u64 gpu_va); + +#endif /* NVGPU_RAMIN_GK20A_H */ diff --git a/drivers/gpu/nvgpu/hal/fifo/ramin_gv11b.c b/drivers/gpu/nvgpu/hal/fifo/ramin_gv11b.c new file mode 100644 index 000000000..205a2035b --- /dev/null +++ b/drivers/gpu/nvgpu/hal/fifo/ramin_gv11b.c @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2015-2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include + +#include + +#include "hal/fifo/ramin_gv11b.h" + +void gv11b_ramin_set_gr_ptr(struct gk20a *g, + struct nvgpu_mem *inst_block, u64 gpu_va) +{ + u32 addr_lo = u64_lo32(gpu_va) >> ram_in_base_shift_v(); + u32 addr_hi = u64_hi32(gpu_va); + + /* point this address to engine_wfi_ptr */ + nvgpu_mem_wr32(g, inst_block, ram_in_engine_wfi_target_w(), + ram_in_engine_cs_wfi_v() | + ram_in_engine_wfi_mode_f(ram_in_engine_wfi_mode_virtual_v()) | + ram_in_engine_wfi_ptr_lo_f(addr_lo)); + + nvgpu_mem_wr32(g, inst_block, ram_in_engine_wfi_ptr_hi_w(), + ram_in_engine_wfi_ptr_hi_f(addr_hi)); +} diff --git a/drivers/gpu/nvgpu/hal/fifo/ramin_gv11b.h b/drivers/gpu/nvgpu/hal/fifo/ramin_gv11b.h new file mode 100644 index 000000000..b0b2bf03f --- /dev/null +++ b/drivers/gpu/nvgpu/hal/fifo/ramin_gv11b.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVGPU_RAMIN_GV11B_H +#define NVGPU_RAMIN_GV11B_H + +#include + +struct gk20a; +struct nvgpu_mem; + +void gv11b_ramin_set_gr_ptr(struct gk20a *g, + struct nvgpu_mem *inst_block, u64 gpu_va); + +#endif /* NVGPU_RAMIN_GV11B_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index f41a679b9..505d937fd 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -1017,6 +1017,10 @@ struct gpu_ops { u32 (*get_syncpt)(struct channel_gk20a *ch); void (*set_syncpt)(struct channel_gk20a *ch, u32 syncpt); } ramfc; + struct { + void (*set_gr_ptr)(struct gk20a *g, + struct nvgpu_mem *inst_block, u64 gpu_va); + } ramin; struct { int (*reschedule)(struct channel_gk20a *ch, bool preempt_next); int (*reschedule_preempt_next_locked)(struct channel_gk20a *ch, diff --git a/drivers/gpu/nvgpu/tu104/hal_tu104.c b/drivers/gpu/nvgpu/tu104/hal_tu104.c index 4ec056b55..433880657 100644 --- a/drivers/gpu/nvgpu/tu104/hal_tu104.c +++ b/drivers/gpu/nvgpu/tu104/hal_tu104.c @@ -63,6 +63,7 @@ #include "hal/fifo/ramfc_gp10b.h" #include "hal/fifo/ramfc_gv11b.h" #include "hal/fifo/ramfc_tu104.h" +#include "hal/fifo/ramin_gv11b.h" #include "hal/fifo/tsg_gv11b.h" #include "hal/fifo/userd_gk20a.h" #include "hal/fifo/userd_gv11b.h" @@ -1004,6 +1005,9 @@ static const struct gpu_ops tu104_ops = { .get_syncpt = NULL, .set_syncpt = NULL, }, + .ramin = { + .set_gr_ptr = gv11b_ramin_set_gr_ptr, + }, .runlist = { .update_for_channel = gk20a_runlist_update_for_channel, .reload = gk20a_runlist_reload, @@ -1429,6 +1433,7 @@ int tu104_init_hal(struct gk20a *g) gops->engine = tu104_ops.engine; gops->pbdma = tu104_ops.pbdma; gops->ramfc = tu104_ops.ramfc; + gops->ramin = tu104_ops.ramin; gops->runlist = tu104_ops.runlist; gops->userd = tu104_ops.userd; gops->channel = tu104_ops.channel;