nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-22 17:36:20 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: unit: Add ACR DBG/PROD bins.

Browse Source 
This patch adds acr_ucode_dbg/prod.bin
The two new bin files are copies of the TOT acr_ucode.bin. They will
act as placeholders till acr ucode with UCODE encryption gets production
signed.

This change also adds a check to select ACR ucode based on board type.
Note: This support is added only for t19x.

P4CL 27814148

Bug 2672836

Change-Id: Ib2f9fc2b23a8c50480a07baa130851c94533f345
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2270657
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
smadhavan
2019-12-30 15:35:33 +05:30
committed by Alex Waterman
parent 2db5c623c4
commit 26ce83862f
4 changed files with 20 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
userspace/Makefile.tmk
View File

@@ -1,6 +1,6 @@
################################### tell Emacs this is a -*- makefile-gmake -*- ################################### tell Emacs this is a -*- makefile-gmake -*-
# #
# Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. # Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
# #
# Permission is hereby granted, free of charge, to any person obtaining a # Permission is hereby granted, free of charge, to any person obtaining a
# copy of this software and associated documentation files (the "Software"), # copy of this software and associated documentation files (the "Software"),
@@ -67,7 +67,8 @@ NV_FECS_IMG=fecs.bin
NV_FECS_SIG_IMG=fecs_sig.bin NV_FECS_SIG_IMG=fecs_sig.bin
NV_GPCCS_IMG=gpccs.bin NV_GPCCS_IMG=gpccs.bin
NV_GPCCS_SIG_IMG=gpccs_sig.bin NV_GPCCS_SIG_IMG=gpccs_sig.bin
NV_ACR_UCODE_IMG=acr_ucode.bin NV_ACR_UCODE_PROD_IMG=acr_ucode_prod.bin
NV_ACR_UCODE_DBG_IMG=acr_ucode_dbg.bin
NV_PMU_BL_IMG=pmu_bl.bin NV_PMU_BL_IMG=pmu_bl.bin
NV_COMPONENT_SYSTEMIMAGE_DIR := $(NV_SYSTEMIMAGE_TEST_EXECUTABLE_DIR)/nvgpu_unit NV_COMPONENT_SYSTEMIMAGE_DIR := $(NV_SYSTEMIMAGE_TEST_EXECUTABLE_DIR)/nvgpu_unit
NV_UNIT_REQ_FIRMWARE_DIR := $(NV_COMPONENT_SYSTEMIMAGE_DIR)/firmware NV_UNIT_REQ_FIRMWARE_DIR := $(NV_COMPONENT_SYSTEMIMAGE_DIR)/firmware
@@ -80,7 +81,8 @@ systemimage:: $(NV_COMPONENT_SYSTEMIMAGE_DIR) $(NV_COMPONENT_SYSTEMIMAGE_DIR)/$(
$(NV_UNIT_REQ_FIRMWARE_DIR)/$(NV_FECS_SIG_IMG) \ $(NV_UNIT_REQ_FIRMWARE_DIR)/$(NV_FECS_SIG_IMG) \
$(NV_UNIT_REQ_FIRMWARE_DIR)/$(NV_GPCCS_IMG) \ $(NV_UNIT_REQ_FIRMWARE_DIR)/$(NV_GPCCS_IMG) \
$(NV_UNIT_REQ_FIRMWARE_DIR)/$(NV_GPCCS_SIG_IMG) \ $(NV_UNIT_REQ_FIRMWARE_DIR)/$(NV_GPCCS_SIG_IMG) \
$(NV_UNIT_REQ_FIRMWARE_DIR)/$(NV_ACR_UCODE_IMG) \ $(NV_UNIT_REQ_FIRMWARE_DIR)/$(NV_ACR_UCODE_PROD_IMG) \
$(NV_UNIT_REQ_FIRMWARE_DIR)/$(NV_ACR_UCODE_DBG_IMG) \
$(NV_UNIT_REQ_FIRMWARE_DIR)/$(NV_PMU_BL_IMG) $(NV_UNIT_REQ_FIRMWARE_DIR)/$(NV_PMU_BL_IMG)
#make the output directory #make the output directory
@@ -109,7 +111,9 @@ $(NV_UNIT_REQ_FIRMWARE_DIR)/$(NV_GPCCS_IMG) : $(NV_COMPONENT_DIR)/firmware/$(NV_
$(CP) $< $@ $(CP) $< $@
$(NV_UNIT_REQ_FIRMWARE_DIR)/$(NV_GPCCS_SIG_IMG) : $(NV_COMPONENT_DIR)/firmware/$(NV_GPCCS_SIG_IMG) $(NV_UNIT_REQ_FIRMWARE_DIR) $(NV_UNIT_REQ_FIRMWARE_DIR)/$(NV_GPCCS_SIG_IMG) : $(NV_COMPONENT_DIR)/firmware/$(NV_GPCCS_SIG_IMG) $(NV_UNIT_REQ_FIRMWARE_DIR)
$(CP) $< $@ $(CP) $< $@
$(NV_UNIT_REQ_FIRMWARE_DIR)/$(NV_ACR_UCODE_IMG) : $(NV_COMPONENT_DIR)/firmware/$(NV_ACR_UCODE_IMG) $(NV_UNIT_REQ_FIRMWARE_DIR) $(NV_UNIT_REQ_FIRMWARE_DIR)/$(NV_ACR_UCODE_PROD_IMG) : $(NV_COMPONENT_DIR)/firmware/$(NV_ACR_UCODE_PROD_IMG) $(NV_UNIT_REQ_FIRMWARE_DIR)
$(CP) $< $@
$(NV_UNIT_REQ_FIRMWARE_DIR)/$(NV_ACR_UCODE_DBG_IMG) : $(NV_COMPONENT_DIR)/firmware/$(NV_ACR_UCODE_DBG_IMG) $(NV_UNIT_REQ_FIRMWARE_DIR)
$(CP) $< $@ $(CP) $< $@
$(NV_UNIT_REQ_FIRMWARE_DIR)/$(NV_PMU_BL_IMG) : $(NV_COMPONENT_DIR)/firmware/$(NV_PMU_BL_IMG) $(NV_UNIT_REQ_FIRMWARE_DIR) $(NV_UNIT_REQ_FIRMWARE_DIR)/$(NV_PMU_BL_IMG) : $(NV_COMPONENT_DIR)/firmware/$(NV_PMU_BL_IMG) $(NV_UNIT_REQ_FIRMWARE_DIR)
$(CP) $< $@ $(CP) $< $@

BIN
userspace/firmware/acr_ucode_dbg.bin Normal file
View File

Binary file not shown.

BIN
userspace/firmware/acr_ucode_prod.bin Normal file
View File

Binary file not shown.

12
userspace/units/falcon/falcon_tests/falcon.c
View File

@@ -1183,10 +1183,18 @@ int test_falcon_bootstrap(struct unit_module *m, struct gk20a *g, void *__args)
} }
#endif #endif
acr_fw = nvgpu_request_firmware(g, HSBIN_ACR_UCODE_IMAGE, 0); if (!g->ops.pmu.is_debug_mode_enabled(g)) {
acr_fw = nvgpu_request_firmware(g, HSBIN_ACR_PROD_UCODE, 0);
if (acr_fw == NULL) { if (acr_fw == NULL) {
unit_return_fail(m, "%s ucode get fail for %s", unit_return_fail(m, "%s ucode get fail for %s",
HSBIN_ACR_UCODE_IMAGE, g->name); HSBIN_ACR_PROD_UCODE, g->name);
}
} else {
acr_fw = nvgpu_request_firmware(g, HSBIN_ACR_DBG_UCODE, 0);
if (acr_fw == NULL) {
unit_return_fail(m, "%s ucode get fail for %s",
HSBIN_ACR_DBG_UCODE, g->name);
}
} }
hs_bin_hdr = (struct bin_hdr *)(void *)acr_fw->data; hs_bin_hdr = (struct bin_hdr *)(void *)acr_fw->data;