diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 93e30e3dc..55793ba7d 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -449,6 +449,7 @@ nvgpu-y += \ common/init/hal_init.o \ common/sec2/sec2.o \ common/sec2/sec2_ipc.o \ + common/sec2/sec2_queue.o \ common/io/io.o \ common/power_features/power_features.o \ common/power_features/cg/cg.o \ diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources index f8ded795c..384cf2638 100644 --- a/drivers/gpu/nvgpu/Makefile.sources +++ b/drivers/gpu/nvgpu/Makefile.sources @@ -161,6 +161,7 @@ srcs += common/sim.c \ common/acr/acr_sw_tu104.c \ common/sec2/sec2.c \ common/sec2/sec2_ipc.c \ + common/sec2/sec2_queue.c \ common/ptimer/ptimer.c \ common/sync/channel_sync.c \ common/sync/channel_sync_syncpt.c \ diff --git a/drivers/gpu/nvgpu/common/sec2/sec2.c b/drivers/gpu/nvgpu/common/sec2/sec2.c index 584051bf8..cba87a7aa 100644 --- a/drivers/gpu/nvgpu/common/sec2/sec2.c +++ b/drivers/gpu/nvgpu/common/sec2/sec2.c @@ -25,82 +25,9 @@ #include #include #include +#include #include #include -#include - -/* sec2 falcon queue init */ -int nvgpu_sec2_queue_init(struct nvgpu_sec2 *sec2, u32 id, - struct sec2_init_msg_sec2_init *init) -{ - struct gk20a *g = sec2->g; - struct nvgpu_engine_mem_queue_params params = {0}; - u32 queue_log_id = 0; - u32 oflag = 0; - int err = 0; - - if (id == SEC2_NV_CMDQ_LOG_ID) { - /* - * set OFLAG_WRITE for command queue - * i.e, push from nvgpu & - * pop form falcon ucode - */ - oflag = OFLAG_WRITE; - } else if (id == SEC2_NV_MSGQ_LOG_ID) { - /* - * set OFLAG_READ for message queue - * i.e, push from falcon ucode & - * pop form nvgpu - */ - oflag = OFLAG_READ; - } else { - nvgpu_err(g, "invalid queue-id %d", id); - err = -EINVAL; - goto exit; - } - - /* init queue parameters */ - queue_log_id = init->q_info[id].queue_log_id; - - params.g = g; - params.flcn_id = FALCON_ID_SEC2; - params.id = queue_log_id; - params.index = init->q_info[id].queue_phy_id; - params.offset = init->q_info[id].queue_offset; - params.position = init->q_info[id].queue_offset; - params.size = init->q_info[id].queue_size; - params.oflag = oflag; - params.queue_head = g->ops.sec2.sec2_queue_head; - params.queue_tail = g->ops.sec2.sec2_queue_tail; - params.queue_type = QUEUE_TYPE_EMEM; - - err = nvgpu_engine_mem_queue_init(&sec2->queue[queue_log_id], - params); - if (err != 0) { - nvgpu_err(g, "queue-%d init failed", queue_log_id); - } - -exit: - return err; -} - -void nvgpu_sec2_queue_free(struct nvgpu_sec2 *sec2, u32 id) -{ - struct gk20a *g = sec2->g; - - if (!(id == SEC2_NV_CMDQ_LOG_ID) && !(id == SEC2_NV_MSGQ_LOG_ID)) { - nvgpu_err(g, "invalid queue-id %d", id); - goto exit; - } - - if (sec2->queue[id] == NULL) { - goto exit; - } - - nvgpu_engine_mem_queue_free(&sec2->queue[id]); -exit: - return; -} static void sec2_seq_init(struct nvgpu_sec2 *sec2) { @@ -191,7 +118,6 @@ int nvgpu_init_sec2_support(struct gk20a *g) int nvgpu_sec2_destroy(struct gk20a *g) { struct nvgpu_sec2 *sec2 = &g->sec2; - u32 i = 0; nvgpu_log_fn(g, " "); @@ -199,9 +125,7 @@ int nvgpu_sec2_destroy(struct gk20a *g) sec2->isr_enabled = false; nvgpu_mutex_release(&sec2->isr_mutex); - for (i = 0; i < SEC2_QUEUE_NUM; i++) { - nvgpu_sec2_queue_free(sec2, i); - } + nvgpu_sec2_queues_free(g, sec2->queues); sec2->sec2_ready = false; diff --git a/drivers/gpu/nvgpu/common/sec2/sec2_ipc.c b/drivers/gpu/nvgpu/common/sec2/sec2_ipc.c index f2a781d5b..68eb44543 100644 --- a/drivers/gpu/nvgpu/common/sec2/sec2_ipc.c +++ b/drivers/gpu/nvgpu/common/sec2/sec2_ipc.c @@ -27,9 +27,10 @@ #include #include #include +#include +#include #include #include -#include static int sec2_seq_acquire(struct nvgpu_sec2 *sec2, struct sec2_sequence **pseq) @@ -84,19 +85,18 @@ static bool sec2_validate_cmd(struct nvgpu_sec2 *sec2, struct nv_flcn_cmd_sec2 *cmd, u32 queue_id) { struct gk20a *g = sec2->g; - struct nvgpu_engine_mem_queue *queue; u32 queue_size; if (queue_id != SEC2_NV_CMDQ_LOG_ID) { goto invalid_cmd; } - queue = sec2->queue[queue_id]; if (cmd->hdr.size < PMU_CMD_HDR_SIZE) { goto invalid_cmd; } - queue_size = nvgpu_engine_mem_queue_get_size(queue); + queue_size = nvgpu_sec2_queue_get_size(sec2->queues, queue_id); + if (cmd->hdr.size > (queue_size >> 1)) { goto invalid_cmd; } @@ -120,18 +120,16 @@ static int sec2_write_cmd(struct nvgpu_sec2 *sec2, u32 timeout_ms) { struct gk20a *g = sec2->g; - struct nvgpu_engine_mem_queue *queue; struct nvgpu_timeout timeout; int err; nvgpu_log_fn(g, " "); - queue = sec2->queue[queue_id]; nvgpu_timeout_init(g, &timeout, timeout_ms, NVGPU_TIMER_CPU_TIMER); do { - err = nvgpu_engine_mem_queue_push(&g->sec2.flcn, queue, cmd, - cmd->hdr.size); + err = nvgpu_sec2_queue_push(sec2->queues, queue_id, &sec2->flcn, + cmd, cmd->hdr.size); if ((err == -EAGAIN) && (nvgpu_timeout_expired(&timeout) == 0)) { nvgpu_usleep_range(1000U, 2000U); } else { @@ -244,53 +242,29 @@ static int sec2_handle_event(struct nvgpu_sec2 *sec2, return err; } -static bool sec2_engine_mem_queue_read(struct nvgpu_sec2 *sec2, - struct nvgpu_engine_mem_queue *queue, void *data, - u32 bytes_to_read, int *status) -{ - struct gk20a *g = sec2->g; - u32 bytes_read; - int err; - - err = nvgpu_engine_mem_queue_pop(&sec2->flcn, queue, data, - bytes_to_read, &bytes_read); - if (err != 0) { - nvgpu_err(g, "fail to read msg: err %d", err); - *status = err; - return false; - } - if (bytes_read != bytes_to_read) { - nvgpu_err(g, "fail to read requested bytes: 0x%x != 0x%x", - bytes_to_read, bytes_read); - *status = -EINVAL; - return false; - } - - return true; -} - static bool sec2_read_message(struct nvgpu_sec2 *sec2, u32 queue_id, struct nv_flcn_msg_sec2 *msg, int *status) { - struct nvgpu_engine_mem_queue *queue = sec2->queue[queue_id]; struct gk20a *g = sec2->g; u32 read_size; int err; *status = 0; - if (nvgpu_engine_mem_queue_is_empty(queue)) { + if (nvgpu_sec2_queue_is_empty(sec2->queues, queue_id)) { return false; } - if (!sec2_engine_mem_queue_read(sec2, queue, &msg->hdr, - PMU_MSG_HDR_SIZE, status)) { + if (!nvgpu_sec2_queue_read(g, sec2->queues, queue_id, + &sec2->flcn, &msg->hdr, + PMU_MSG_HDR_SIZE, status)) { nvgpu_err(g, "fail to read msg from queue %d", queue_id); goto clean_up; } if (msg->hdr.unit_id == NV_SEC2_UNIT_REWIND) { - err = nvgpu_engine_mem_queue_rewind(&sec2->flcn, queue); + err = nvgpu_sec2_queue_rewind(&sec2->flcn, + sec2->queues, queue_id); if (err != 0) { nvgpu_err(g, "fail to rewind queue %d", queue_id); *status = err; @@ -298,8 +272,9 @@ static bool sec2_read_message(struct nvgpu_sec2 *sec2, } /* read again after rewind */ - if (!sec2_engine_mem_queue_read(sec2, queue, &msg->hdr, - PMU_MSG_HDR_SIZE, status)) { + if (!nvgpu_sec2_queue_read(g, sec2->queues, queue_id, + &sec2->flcn, &msg->hdr, + PMU_MSG_HDR_SIZE, status)) { nvgpu_err(g, "fail to read msg from queue %d", queue_id); goto clean_up; @@ -315,8 +290,9 @@ static bool sec2_read_message(struct nvgpu_sec2 *sec2, if (msg->hdr.size > PMU_MSG_HDR_SIZE) { read_size = msg->hdr.size - PMU_MSG_HDR_SIZE; - if (!sec2_engine_mem_queue_read(sec2, queue, &msg->msg, - read_size, status)) { + if (!nvgpu_sec2_queue_read(g, sec2->queues, queue_id, + &sec2->flcn, &msg->msg, + read_size, status)) { nvgpu_err(g, "fail to read msg from queue %d", queue_id); goto clean_up; @@ -334,7 +310,7 @@ static int sec2_process_init_msg(struct nvgpu_sec2 *sec2, { struct gk20a *g = sec2->g; struct sec2_init_msg_sec2_init *sec2_init; - u32 i, j, tail = 0; + u32 tail = 0; int err = 0; g->ops.sec2.msgq_tail(g, sec2, &tail, QUEUE_GET); @@ -368,15 +344,9 @@ static int sec2_process_init_msg(struct nvgpu_sec2 *sec2, sec2_init = &msg->msg.init.sec2_init; - for (i = 0; i < SEC2_QUEUE_NUM; i++) { - err = nvgpu_sec2_queue_init(sec2, i, sec2_init); - if (err != 0) { - for (j = 0; j < i; j++) { - nvgpu_sec2_queue_free(sec2, j); - } - nvgpu_err(g, "SEC2 queue init failed"); - return err; - } + err = nvgpu_sec2_queues_init(g, sec2->queues, sec2_init); + if (err != 0) { + return err; } if (!nvgpu_alloc_initialized(&sec2->dmem)) { diff --git a/drivers/gpu/nvgpu/common/sec2/sec2_queue.c b/drivers/gpu/nvgpu/common/sec2/sec2_queue.c new file mode 100644 index 000000000..84eee1e4d --- /dev/null +++ b/drivers/gpu/nvgpu/common/sec2/sec2_queue.c @@ -0,0 +1,191 @@ +/* + * Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include +#include +#include +#include + +/* sec2 falcon queue init */ +static int sec2_queue_init(struct gk20a *g, + struct nvgpu_engine_mem_queue **queues, u32 id, + struct sec2_init_msg_sec2_init *init) +{ + struct nvgpu_engine_mem_queue_params params = {0}; + u32 queue_log_id = 0; + u32 oflag = 0; + int err = 0; + + if (id == SEC2_NV_CMDQ_LOG_ID) { + /* + * set OFLAG_WRITE for command queue + * i.e, push from nvgpu & + * pop form falcon ucode + */ + oflag = OFLAG_WRITE; + } else if (id == SEC2_NV_MSGQ_LOG_ID) { + /* + * set OFLAG_READ for message queue + * i.e, push from falcon ucode & + * pop form nvgpu + */ + oflag = OFLAG_READ; + } else { + nvgpu_err(g, "invalid queue-id %d", id); + err = -EINVAL; + goto exit; + } + + /* init queue parameters */ + queue_log_id = init->q_info[id].queue_log_id; + + params.g = g; + params.flcn_id = FALCON_ID_SEC2; + params.id = queue_log_id; + params.index = init->q_info[id].queue_phy_id; + params.offset = init->q_info[id].queue_offset; + params.position = init->q_info[id].queue_offset; + params.size = init->q_info[id].queue_size; + params.oflag = oflag; + params.queue_head = g->ops.sec2.sec2_queue_head; + params.queue_tail = g->ops.sec2.sec2_queue_tail; + params.queue_type = QUEUE_TYPE_EMEM; + + err = nvgpu_engine_mem_queue_init(&queues[queue_log_id], + params); + if (err != 0) { + nvgpu_err(g, "queue-%d init failed", queue_log_id); + } + +exit: + return err; +} + +static void sec2_queue_free(struct gk20a *g, + struct nvgpu_engine_mem_queue **queues, u32 id) +{ + if (!(id == SEC2_NV_CMDQ_LOG_ID) && !(id == SEC2_NV_MSGQ_LOG_ID)) { + nvgpu_err(g, "invalid queue-id %d", id); + goto exit; + } + + if (queues[id] == NULL) { + goto exit; + } + + nvgpu_engine_mem_queue_free(&queues[id]); +exit: + return; +} + +int nvgpu_sec2_queues_init(struct gk20a *g, + struct nvgpu_engine_mem_queue **queues, + struct sec2_init_msg_sec2_init *init) +{ + u32 i, j; + int err; + + for (i = 0; i < SEC2_QUEUE_NUM; i++) { + err = sec2_queue_init(g, queues, i, init); + if (err != 0) { + for (j = 0; j < i; j++) { + sec2_queue_free(g, queues, j); + } + nvgpu_err(g, "SEC2 queue init failed"); + return err; + } + } + + return 0; +} + +void nvgpu_sec2_queues_free(struct gk20a *g, + struct nvgpu_engine_mem_queue **queues) +{ + u32 i; + + for (i = 0; i < SEC2_QUEUE_NUM; i++) { + sec2_queue_free(g, queues, i); + } +} + +u32 nvgpu_sec2_queue_get_size(struct nvgpu_engine_mem_queue **queues, + u32 queue_id) +{ + return nvgpu_engine_mem_queue_get_size(queues[queue_id]); +} + +int nvgpu_sec2_queue_push(struct nvgpu_engine_mem_queue **queues, + u32 queue_id, struct nvgpu_falcon *flcn, + struct nv_flcn_cmd_sec2 *cmd, u32 size) +{ + struct nvgpu_engine_mem_queue *queue; + + queue = queues[queue_id]; + return nvgpu_engine_mem_queue_push(flcn, queue, cmd, size); +} + +bool nvgpu_sec2_queue_is_empty(struct nvgpu_engine_mem_queue **queues, + u32 queue_id) +{ + struct nvgpu_engine_mem_queue *queue = queues[queue_id]; + + return nvgpu_engine_mem_queue_is_empty(queue); +} + +bool nvgpu_sec2_queue_read(struct gk20a *g, + struct nvgpu_engine_mem_queue **queues, + u32 queue_id, struct nvgpu_falcon *flcn, void *data, + u32 bytes_to_read, int *status) +{ + struct nvgpu_engine_mem_queue *queue = queues[queue_id]; + u32 bytes_read; + int err; + + err = nvgpu_engine_mem_queue_pop(flcn, queue, data, + bytes_to_read, &bytes_read); + if (err != 0) { + nvgpu_err(g, "fail to read msg: err %d", err); + *status = err; + return false; + } + if (bytes_read != bytes_to_read) { + nvgpu_err(g, "fail to read requested bytes: 0x%x != 0x%x", + bytes_to_read, bytes_read); + *status = -EINVAL; + return false; + } + + return true; +} + +int nvgpu_sec2_queue_rewind(struct nvgpu_falcon *flcn, + struct nvgpu_engine_mem_queue **queues, + u32 queue_id) +{ + struct nvgpu_engine_mem_queue *queue = queues[queue_id]; + + return nvgpu_engine_mem_queue_rewind(flcn, queue); +} diff --git a/drivers/gpu/nvgpu/include/nvgpu/sec2.h b/drivers/gpu/nvgpu/include/nvgpu/sec2.h index dbd968039..83287608a 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/sec2.h +++ b/drivers/gpu/nvgpu/include/nvgpu/sec2.h @@ -72,7 +72,7 @@ struct nvgpu_sec2 { struct nvgpu_falcon flcn; u32 falcon_id; - struct nvgpu_engine_mem_queue *queue[SEC2_QUEUE_NUM]; + struct nvgpu_engine_mem_queue *queues[SEC2_QUEUE_NUM]; struct sec2_sequence *seq; unsigned long sec2_seq_tbl[SEC2_SEQ_TBL_SIZE]; @@ -110,8 +110,5 @@ int nvgpu_sec2_bootstrap_ls_falcons(struct gk20a *g, struct nvgpu_sec2 *sec2, int nvgpu_init_sec2_setup_sw(struct gk20a *g, struct nvgpu_sec2 *sec2); int nvgpu_init_sec2_support(struct gk20a *g); int nvgpu_sec2_destroy(struct gk20a *g); -int nvgpu_sec2_queue_init(struct nvgpu_sec2 *sec2, u32 id, - struct sec2_init_msg_sec2_init *init); -void nvgpu_sec2_queue_free(struct nvgpu_sec2 *sec2, u32 id); #endif /* NVGPU_SEC2_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/sec2/queue.h b/drivers/gpu/nvgpu/include/nvgpu/sec2/queue.h new file mode 100644 index 000000000..8480169d5 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/sec2/queue.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVGPU_SEC2_QUEUE_H +#define NVGPU_SEC2_QUEUE_H + +#include + +struct gk20a; +struct nvgpu_falcon; +struct nv_flcn_cmd_sec2; +struct nvgpu_engine_mem_queue; +struct sec2_init_msg_sec2_init; + +int nvgpu_sec2_queues_init(struct gk20a *g, + struct nvgpu_engine_mem_queue **queues, + struct sec2_init_msg_sec2_init *init); +void nvgpu_sec2_queues_free(struct gk20a *g, + struct nvgpu_engine_mem_queue **queues); +u32 nvgpu_sec2_queue_get_size(struct nvgpu_engine_mem_queue **queues, + u32 queue_id); +int nvgpu_sec2_queue_push(struct nvgpu_engine_mem_queue **queues, + u32 queue_id, struct nvgpu_falcon *flcn, + struct nv_flcn_cmd_sec2 *cmd, u32 size); +bool nvgpu_sec2_queue_is_empty(struct nvgpu_engine_mem_queue **queues, + u32 queue_id); +bool nvgpu_sec2_queue_read(struct gk20a *g, + struct nvgpu_engine_mem_queue **queues, + u32 queue_id, struct nvgpu_falcon *flcn, void *data, + u32 bytes_to_read, int *status); +int nvgpu_sec2_queue_rewind(struct nvgpu_falcon *flcn, + struct nvgpu_engine_mem_queue **queues, + u32 queue_id); + +#endif /* NVGPU_SEC2_QUEUE_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/sec2/queue_cmn.h b/drivers/gpu/nvgpu/include/nvgpu/sec2/queue_cmn.h new file mode 100644 index 000000000..b6c73ce2a --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/sec2/queue_cmn.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVGPU_SEC2_CMN_H +#define NVGPU_SEC2_CMN_H + +/* + * Defines the logical queue IDs that must be used when submitting commands + * to or reading messages from SEC2. The identifiers must begin with zero and + * should increment sequentially. _CMDQ_LOG_ID__LAST must always be set to the + * last command queue identifier. _NUM must always be set to the last + * identifier plus one. + */ +#define SEC2_NV_CMDQ_LOG_ID 0U +#define SEC2_NV_CMDQ_LOG_ID__LAST 0U +#define SEC2_NV_MSGQ_LOG_ID 1U +#define SEC2_QUEUE_NUM 2U + +#endif /* NVGPU_SEC2_CMN_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/sec2if/sec2_if_sec2.h b/drivers/gpu/nvgpu/include/nvgpu/sec2if/sec2_if_sec2.h index c895c418f..a29451165 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/sec2if/sec2_if_sec2.h +++ b/drivers/gpu/nvgpu/include/nvgpu/sec2if/sec2_if_sec2.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -23,6 +23,9 @@ #ifndef NVGPU_SEC2_IF_SEC2_H #define NVGPU_SEC2_IF_SEC2_H +#include +#include + /* * SEC2 Command/Message Interfaces - SEC2 Management */ @@ -37,18 +40,6 @@ enum NV_SEC2_INIT_MSG_ID_SEC2_INIT = 0U, }; -/* - * Defines the logical queue IDs that must be used when submitting commands - * to or reading messages from SEC2. The identifiers must begin with zero and - * should increment sequentially. _CMDQ_LOG_ID__LAST must always be set to the - * last command queue identifier. _NUM must always be set to the last - * identifier plus one. - */ -#define SEC2_NV_CMDQ_LOG_ID 0U -#define SEC2_NV_CMDQ_LOG_ID__LAST 0U -#define SEC2_NV_MSGQ_LOG_ID 1U -#define SEC2_QUEUE_NUM 2U - struct sec2_init_msg_sec2_init { u8 msg_type; u8 num_queues; diff --git a/drivers/gpu/nvgpu/tu104/sec2_tu104.c b/drivers/gpu/nvgpu/tu104/sec2_tu104.c index c6b10a646..310bf8693 100644 --- a/drivers/gpu/nvgpu/tu104/sec2_tu104.c +++ b/drivers/gpu/nvgpu/tu104/sec2_tu104.c @@ -412,7 +412,7 @@ void tu104_sec2_isr(struct gk20a *g) gk20a_writel(g, psec_falcon_irqsclr_r(), intr); if (recheck) { - queue = sec2->queue[SEC2_NV_MSGQ_LOG_ID]; + queue = sec2->queues[SEC2_NV_MSGQ_LOG_ID]; if (!nvgpu_engine_mem_queue_is_empty(queue)) { gk20a_writel(g, psec_falcon_irqsset_r(), psec_falcon_irqsset_swgen0_set_f());