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gpu: nvgpu: fix header guards in common.gr unit

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Fix header guard names as per convention for below common.gr headers :
common/gr/gr_falcon_priv.h
common/gr/zbc_priv.h
include/nvgpu/gr/ctx.h

Jira NVGPU-5005

Change-Id: I68947ea3e8f4ddbcd43be8d8717eb8ddcc6f5bcb
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2470072
(cherry picked from commit eb044acbafc6d9f735e066d9c7497156f1df13c7)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2478884
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Deepak Nibade
2021-01-13 20:37:58 +05:30
committed by mobile promotions
parent fa952ed71a
commit 27b321e1a9
3 changed files with 12 additions and 12 deletions
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8
drivers/gpu/nvgpu/common/gr/gr_falcon_priv.h
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@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -20,8 +20,8 @@
* DEALINGS IN THE SOFTWARE. * DEALINGS IN THE SOFTWARE.
*/ */
#ifndef GR_FALCON_PRIV_H #ifndef NVGPU_GR_FALCON_PRIV_H
#define GR_FALCON_PRIV_H #define NVGPU_GR_FALCON_PRIV_H
#include <nvgpu/types.h> #include <nvgpu/types.h>
#include <nvgpu/nvgpu_mem.h> #include <nvgpu/nvgpu_mem.h>
@@ -209,4 +209,4 @@ struct nvgpu_gr_falcon {
struct nvgpu_gr_falcon_query_sizes sizes; struct nvgpu_gr_falcon_query_sizes sizes;
}; };
#endif /* GR_FALCON_PRIV_H */ #endif /* NVGPU_GR_FALCON_PRIV_H */

8
drivers/gpu/nvgpu/common/gr/zbc_priv.h
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@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -20,8 +20,8 @@
* DEALINGS IN THE SOFTWARE. * DEALINGS IN THE SOFTWARE.
*/ */
#ifndef GR_ZBC_H #ifndef NVGPU_GR_ZBC_PRIV_H
#define GR_ZBC_H #define NVGPU_GR_ZBC_PRIV_H
#include <nvgpu/gr/zbc.h> #include <nvgpu/gr/zbc.h>
@@ -85,5 +85,5 @@ struct nvgpu_gr_zbc {
u32 max_used_stencil_index; /* Max used stencil table index */ u32 max_used_stencil_index; /* Max used stencil table index */
}; };
#endif /* GR_ZBC_H */ #endif /* NVGPU_GR_ZBC_PRIV_H */

8
drivers/gpu/nvgpu/include/nvgpu/gr/ctx.h
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -20,8 +20,8 @@
* DEALINGS IN THE SOFTWARE. * DEALINGS IN THE SOFTWARE.
*/ */
#ifndef NVGPU_INCLUDE_GR_CTX_H #ifndef NVGPU_GR_CTX_H
#define NVGPU_INCLUDE_GR_CTX_H #define NVGPU_GR_CTX_H
#include <nvgpu/types.h> #include <nvgpu/types.h>
#include <nvgpu/nvgpu_mem.h> #include <nvgpu/nvgpu_mem.h>
@@ -612,4 +612,4 @@ bool nvgpu_gr_ctx_desc_dump_ctxsw_stats_on_channel_close(
struct nvgpu_gr_ctx_desc *gr_ctx_desc); struct nvgpu_gr_ctx_desc *gr_ctx_desc);
#endif #endif
#endif /* NVGPU_INCLUDE_GR_CTX_H */ #endif /* NVGPU_GR_CTX_H */