gpu: nvgpu: unit: add tests for common.fifo.engine

Add unit tests for:
- nvgpu_engine_setup_sw
- nvgpu_engine_cleanup_sw
- nvgpu_engine_init_info
- nvgpu_engine_get_ids
- nvgpu_engine_check_valid_id
- nvgpu_engine_get_gr_id
- nvgpu_engine_get_active_eng_info
- nvgpu_engine_enum_from_type
- nvgpu_engine_interrupt_mask
- nvgpu_engine_act_interrupt_mask
- nvgpu_engine_get_all_ce_reset_mask

Jira NVGPU-3693

Change-Id: I8cbaea1918b284ac09a502225fa674f84c08eb8e
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2242701
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

userspace/Makefile.sources

@@ -79,6 +79,7 @@ UNITS :=				\
 	$(UNIT_SRC)/fifo/channel/gk20a	\
 	$(UNIT_SRC)/fifo/channel/gm20b	\
 	$(UNIT_SRC)/fifo/channel/gv11b	\
+	$(UNIT_SRC)/fifo/engine		\
 	$(UNIT_SRC)/fifo/pbdma		\
 	$(UNIT_SRC)/fifo/runlist	\
 	$(UNIT_SRC)/fifo/runlist/gk20a	\

userspace/SWUTS.h

@@ -41,6 +41,7 @@
  *   - @ref SWUTS-fifo-channel-gk20a
  *   - @ref SWUTS-fifo-channel-gm20b
  *   - @ref SWUTS-fifo-channel-gv11b
+ *   - @ref SWUTS-fifo-engine
  *   - @ref SWUTS-fifo-pbdma
  *   - @ref SWUTS-fifo-runlist
  *   - @ref SWUTS-fifo-runlist-gk20a

userspace/SWUTS.sources

@@ -11,6 +11,7 @@ INPUT += ../../../userspace/units/fifo/channel/nvgpu-channel.h
 INPUT += ../../../userspace/units/fifo/channel/gk20a/nvgpu-channel-gk20a.h
 INPUT += ../../../userspace/units/fifo/channel/gm20b/nvgpu-channel-gm20b.h
 INPUT += ../../../userspace/units/fifo/channel/gv11b/nvgpu-channel-gv11b.h
+INPUT += ../../../userspace/units/fifo/engine/nvgpu-engine.h
 INPUT += ../../../userspace/units/fifo/pbdma/nvgpu-pbdma.h
 INPUT += ../../../userspace/units/fifo/runlist/nvgpu-runlist.h
 INPUT += ../../../userspace/units/fifo/runlist/gk20a/nvgpu-runlist-gk20a.h

userspace/units/fifo/engine/Makefile

@@ -0,0 +1,33 @@
+# Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+
+.SUFFIXES:
+
+OBJS   = nvgpu-engine.o
+MODULE = nvgpu-engine
+
+LIB_PATHS += -lnvgpu-fifo
+include ../../Makefile.units
+
+lib$(MODULE).so: fifo
+
+fifo:
+	$(MAKE) -C ..
+

userspace/units/fifo/engine/Makefile.interface.tmk

@@ -0,0 +1,35 @@
+################################### tell Emacs this is a -*- makefile-gmake -*-
+#
+# Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+#
+# tmake for SW Mobile component makefile
+#
+###############################################################################
+
+NVGPU_UNIT_NAME=nvgpu-engine
+
+include $(NV_COMPONENT_DIR)/../../Makefile.units.common.interface.tmk
+
+# Local Variables:
+# indent-tabs-mode: t
+# tab-width: 8
+# End:
+# vi: set tabstop=8 noexpandtab:

userspace/units/fifo/engine/Makefile.tmk

@@ -0,0 +1,40 @@
+################################### tell Emacs this is a -*- makefile-gmake -*-
+#
+# Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+#
+# tmake for SW Mobile component makefile
+#
+###############################################################################
+
+NVGPU_UNIT_NAME = nvgpu-engine
+NVGPU_UNIT_SRCS = nvgpu-engine.c
+
+NVGPU_UNIT_INTERFACE_DIRS := \
+	$(NV_COMPONENT_DIR)/.. \
+	$(NV_SOURCE)/kernel/nvgpu/drivers/gpu/nvgpu
+
+include $(NV_COMPONENT_DIR)/../../Makefile.units.common.tmk
+
+# Local Variables:
+# indent-tabs-mode: t
+# tab-width: 8
+# End:
+# vi: set tabstop=8 noexpandtab:

userspace/units/fifo/engine/nvgpu-engine.c

@@ -0,0 +1,405 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#include <stdlib.h>
+#include <sys/types.h>
+#include <unistd.h>
+
+#include <unit/io.h>
+#include <unit/unit.h>
+
+#include <nvgpu/channel.h>
+#include <nvgpu/channel_sync.h>
+#include <nvgpu/dma.h>
+#include <nvgpu/engines.h>
+#include <nvgpu/tsg.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/runlist.h>
+
+#include "hal/init/hal_gv11b.h"
+
+#include <nvgpu/posix/posix-fault-injection.h>
+
+#include "nvgpu/hw/gv11b/hw_top_gv11b.h"
+
+#include "../nvgpu-fifo.h"
+#include "../nvgpu-fifo-gv11b.h"
+#include "nvgpu-engine.h"
+
+#ifdef ENGINE_UNIT_DEBUG
+#undef unit_verbose
+#define unit_verbose	unit_info
+#else
+#define unit_verbose(unit, msg, ...) \
+	do { \
+		if (0) { \
+			unit_info(unit, msg, ##__VA_ARGS__); \
+		} \
+	} while (0)
+#endif
+
+struct unit_ctx {
+	u32 branches;
+	u32 ce_mask;
+	u32 eng_mask;
+};
+
+struct unit_ctx unit_ctx;
+
+static void subtest_setup(u32 branches)
+{
+	unit_ctx.branches = branches;
+}
+
+#define subtest_pruned	test_fifo_subtest_pruned
+#define branches_str	test_fifo_flags_str
+
+#define assert(cond)	unit_assert(cond, goto done)
+
+#define F_ENGINE_SETUP_SW_ENGINE_INFO_ENOMEM	BIT(0)
+#define F_ENGINE_SETUP_SW_ENGINE_LIST_ENOMEM	BIT(1)
+#define F_ENGINE_SETUP_SW_INIT_INFO_FAIL	BIT(2)
+#define F_ENGINE_SETUP_SW_LAST			BIT(3)
+
+
+static int stub_engine_init_info_EINVAL(struct nvgpu_fifo *f)
+{
+	return -EINVAL;
+}
+
+static int stub_engine_init_info(struct nvgpu_fifo *f)
+{
+	return 0;
+}
+
+int test_engine_setup_sw(struct unit_module *m,
+		struct gk20a *g, void *args)
+{
+	struct gpu_ops gops = g->ops;
+	struct nvgpu_fifo *f = &g->fifo;
+	struct nvgpu_posix_fault_inj *kmem_fi;
+	u32 branches;
+	int ret = UNIT_FAIL;
+	int err;
+	u32 fail = F_ENGINE_SETUP_SW_ENGINE_INFO_ENOMEM |
+		F_ENGINE_SETUP_SW_ENGINE_LIST_ENOMEM |
+		F_ENGINE_SETUP_SW_INIT_INFO_FAIL;
+	const char *labels[] = {
+		"engine_info_nomem",
+		"engine_list_nomem",
+		"init_info_fail",
+	};
+	u32 prune = fail;
+
+	err = test_fifo_setup_gv11b_reg_space(m, g);
+	assert(err == 0);
+
+	gv11b_init_hal(g);
+
+	kmem_fi = nvgpu_kmem_get_fault_injection();
+
+	for (branches = 0U; branches < F_ENGINE_SETUP_SW_LAST; branches++) {
+
+		if (subtest_pruned(branches, prune)) {
+			unit_verbose(m, "%s branches=%s (pruned)\n",
+				__func__, branches_str(branches, labels));
+			continue;
+		}
+		subtest_setup(branches);
+		unit_verbose(m, "%s branches=%s\n", __func__,
+			branches_str(branches, labels));
+
+		nvgpu_posix_enable_fault_injection(kmem_fi, false, 0);
+
+		if (branches & F_ENGINE_SETUP_SW_ENGINE_INFO_ENOMEM) {
+			nvgpu_posix_enable_fault_injection(kmem_fi, true, 0);
+		}
+
+		if (branches & F_ENGINE_SETUP_SW_ENGINE_LIST_ENOMEM) {
+			nvgpu_posix_enable_fault_injection(kmem_fi, true, 1);
+		}
+
+		g->ops.engine.init_info =
+			branches & F_ENGINE_SETUP_SW_INIT_INFO_FAIL ?
+			stub_engine_init_info_EINVAL : stub_engine_init_info;
+
+		err = nvgpu_engine_setup_sw(g);
+
+		if (branches & fail) {
+			assert(err != 0);
+			assert(f->active_engines_list == NULL);
+			assert(f->engine_info == NULL);
+		} else {
+			assert(err == 0);
+			assert(f->active_engines_list != NULL);
+			assert(f->engine_info != NULL);
+			nvgpu_engine_cleanup_sw(g);
+		}
+	}
+
+	ret = UNIT_SUCCESS;
+done:
+	nvgpu_posix_enable_fault_injection(kmem_fi, false, 0);
+	if (ret != UNIT_SUCCESS) {
+		unit_err(m, "%s branches=%s\n", __func__,
+			branches_str(branches, labels));
+	}
+	g->ops = gops;
+	return ret;
+}
+
+#define F_ENGINE_INIT_INFO_GET_DEV_INFO_NULL	BIT(0)
+#define F_ENGINE_INIT_INFO_GET_DEV_INFO_FAIL	BIT(1)
+#define F_ENGINE_INIT_INFO_PBDMA_FIND_FAIL	BIT(2)
+#define F_ENGINE_INIT_INFO_INIT_CE_FAIL		BIT(3)
+#define F_ENGINE_INIT_INFO_LAST			BIT(4)
+
+static int stub_top_get_device_info_EINVAL(struct gk20a *g,
+		struct nvgpu_device_info *dev_info,
+		u32 engine_type, u32 inst_id)
+{
+	return -EINVAL;
+}
+
+static bool stub_pbdma_find_for_runlist_none(struct gk20a *g,
+			u32 runlist_id, u32 *pbdma_id)
+{
+	return false;
+}
+
+static int stub_engine_init_ce_info_EINVAL(struct nvgpu_fifo *f)
+{
+	return -EINVAL;
+}
+
+int test_engine_init_info(struct unit_module *m,
+		struct gk20a *g, void *args)
+{
+	struct gpu_ops gops = g->ops;
+	struct nvgpu_fifo *f = &g->fifo;
+	struct nvgpu_fifo fifo = g->fifo;
+	u32 branches;
+	int ret = UNIT_FAIL;
+	int err;
+	u32 fail =
+		F_ENGINE_INIT_INFO_GET_DEV_INFO_NULL |
+		F_ENGINE_INIT_INFO_GET_DEV_INFO_FAIL |
+		F_ENGINE_INIT_INFO_PBDMA_FIND_FAIL |
+		F_ENGINE_INIT_INFO_INIT_CE_FAIL;
+	const char *labels[] = {
+		"get_dev_info_null",
+		"get_dev_info_fail",
+		"pbdma_find_fail",
+		"init_ce_fail",
+	};
+	u32 prune = fail;
+
+	for (branches = 0U; branches < F_ENGINE_INIT_INFO_LAST; branches++) {
+
+		if (subtest_pruned(branches, prune)) {
+			unit_verbose(m, "%s branches=%s (pruned)\n",
+				__func__, branches_str(branches, labels));
+			continue;
+		}
+		subtest_setup(branches);
+		unit_verbose(m, "%s branches=%s\n", __func__,
+			branches_str(branches, labels));
+
+		if (branches & F_ENGINE_INIT_INFO_GET_DEV_INFO_NULL) {
+			g->ops.top.get_device_info = NULL;
+		} else {
+			g->ops.top.get_device_info =
+				branches & F_ENGINE_INIT_INFO_GET_DEV_INFO_FAIL ?
+					stub_top_get_device_info_EINVAL :
+					gops.top.get_device_info;
+		}
+
+		g->ops.pbdma.find_for_runlist =
+			branches & F_ENGINE_INIT_INFO_PBDMA_FIND_FAIL ?
+				stub_pbdma_find_for_runlist_none :
+				gops.pbdma.find_for_runlist;
+
+		g->ops.engine.init_ce_info =
+			branches & F_ENGINE_INIT_INFO_INIT_CE_FAIL ?
+				stub_engine_init_ce_info_EINVAL :
+				gops.engine.init_ce_info;
+
+		err = nvgpu_engine_init_info(f);
+
+		if (branches & fail) {
+			assert(err != 0);
+		} else {
+			assert(err == 0);
+			assert(f->num_engines > 0);
+		}
+	}
+
+	ret = UNIT_SUCCESS;
+done:
+	if (ret != UNIT_SUCCESS) {
+		unit_err(m, "%s branches=%s\n", __func__,
+			branches_str(branches, labels));
+	}
+	g->ops = gops;
+	g->fifo = fifo;
+	return ret;
+}
+
+#define MAX_ENGINE_IDS	8
+
+int test_engine_ids(struct unit_module *m,
+		struct gk20a *g, void *args)
+{
+	int ret = UNIT_FAIL;
+	enum nvgpu_fifo_engine e;
+	u32 engine_ids[MAX_ENGINE_IDS];
+	u32 n, i;
+	u32 engine_id;
+
+	unit_ctx.ce_mask = 0;
+	unit_ctx.eng_mask = 0;
+
+	assert(nvgpu_engine_check_valid_id(g, U32_MAX) == false);
+
+	assert(nvgpu_engine_get_ids(g, &engine_id, 1, NVGPU_ENGINE_INVAL) == 0);
+
+	for (e = NVGPU_ENGINE_GR; e < NVGPU_ENGINE_INVAL; e++) {
+
+		n = nvgpu_engine_get_ids(g, engine_ids, MAX_ENGINE_IDS, e);
+		assert(n > 0);
+		for (i = 0; i < n; i++) {
+			engine_id = engine_ids[i];
+
+			assert(nvgpu_engine_check_valid_id(g, engine_id) == true);
+			unit_ctx.eng_mask |= BIT(engine_id);
+			if (e == NVGPU_ENGINE_ASYNC_CE || e == NVGPU_ENGINE_GRCE) {
+				unit_ctx.ce_mask |= BIT(engine_id);
+			}
+		}
+	}
+
+	assert(nvgpu_engine_get_ids(g, &engine_id, 1, NVGPU_ENGINE_GR) == 1);
+	assert(engine_id == nvgpu_engine_get_gr_id(g));
+	assert(unit_ctx.eng_mask != 0);
+	assert(unit_ctx.ce_mask != 0);
+
+	ret = UNIT_SUCCESS;
+done:
+	return ret;
+}
+
+int test_engine_get_active_eng_info(struct unit_module *m,
+		struct gk20a *g, void *args)
+{
+	int ret = UNIT_FAIL;
+	u32 engine_id;
+	struct nvgpu_engine_info *info;
+	u32 eng_mask;
+	struct nvgpu_fifo *f = &g->fifo;
+
+	for (engine_id = 0; engine_id < f->max_engines; engine_id++) {
+
+		unit_verbose(m, "engine_id=%u\n", engine_id);
+		info = nvgpu_engine_get_active_eng_info(g, engine_id);
+		if (nvgpu_engine_check_valid_id(g, engine_id)) {
+			assert(info != NULL);
+			assert(info->engine_id == engine_id);
+			eng_mask |= BIT(engine_id);
+		} else {
+			assert(info == NULL);
+		}
+	}
+	unit_verbose(m, "eng_mask=%x\n", eng_mask);
+	unit_verbose(m, "unit_ctx.eng_mask=%x\n", unit_ctx.eng_mask);
+	assert(eng_mask == unit_ctx.eng_mask);
+
+	ret = UNIT_SUCCESS;
+done:
+	return ret;
+}
+
+int test_engine_enum_from_type(struct unit_module *m,
+		struct gk20a *g, void *args)
+{
+	int ret = UNIT_FAIL;
+	int engine_enum;
+
+	engine_enum = nvgpu_engine_enum_from_type(g,
+		top_device_info_type_enum_graphics_v());
+	assert(engine_enum == NVGPU_ENGINE_GR);
+
+	engine_enum = nvgpu_engine_enum_from_type(g,
+		top_device_info_type_enum_lce_v());
+	assert(engine_enum == NVGPU_ENGINE_ASYNC_CE);
+
+	engine_enum = nvgpu_engine_enum_from_type(g, 0xff);
+	assert(engine_enum == NVGPU_ENGINE_INVAL);
+
+	ret = UNIT_SUCCESS;
+done:
+	return ret;
+}
+
+int test_engine_interrupt_mask(struct unit_module *m,
+		struct gk20a *g, void *args)
+{
+	int ret = UNIT_FAIL;
+	u32 intr_mask = nvgpu_engine_interrupt_mask(g);
+	u32 all_mask = 0U;
+	u32 ce_reset_mask;
+	u32 mask;
+	u32 engine_id;
+	struct nvgpu_fifo *f = &g->fifo;
+
+	assert(intr_mask != 0U);
+	for (engine_id = 0; engine_id < f->max_engines; engine_id++) {
+		unit_verbose(m, "engine_id=%u\n", engine_id);
+		mask = nvgpu_engine_act_interrupt_mask(g, engine_id);
+		if (nvgpu_engine_check_valid_id(g, engine_id)) {
+			assert(mask != 0);
+			assert((mask & intr_mask) == mask);
+			all_mask |= mask;
+		} else {
+			assert(mask == 0);
+		}
+	}
+	assert(intr_mask == all_mask);
+
+	ce_reset_mask = nvgpu_engine_get_all_ce_reset_mask(g);
+	assert(ce_reset_mask != 0);;
+
+	ret = UNIT_SUCCESS;
+done:
+	return ret;
+}
+
+struct unit_module_test nvgpu_engine_tests[] = {
+	UNIT_TEST(setup_sw, test_engine_setup_sw, &unit_ctx, 0),
+	UNIT_TEST(init_support, test_fifo_init_support, &unit_ctx, 0),
+	UNIT_TEST(init_info, test_engine_init_info, &unit_ctx, 0),
+	UNIT_TEST(ids, test_engine_ids, &unit_ctx, 0),
+	UNIT_TEST(get_active_eng_info, test_engine_get_active_eng_info, &unit_ctx, 0),
+	UNIT_TEST(enum_from_type, test_engine_enum_from_type, &unit_ctx, 0),
+	UNIT_TEST(interrupt_mask, test_engine_interrupt_mask, &unit_ctx, 0),
+	UNIT_TEST(remove_support, test_fifo_remove_support, &unit_ctx, 0),
+};
+
+UNIT_MODULE(nvgpu_engine, nvgpu_engine_tests, UNIT_PRIO_NVGPU_TEST);

userspace/units/fifo/engine/nvgpu-engine.h

@@ -0,0 +1,187 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+
+#ifndef UNIT_NVGPU_ENGINE_H
+#define UNIT_NVGPU_ENGINE_H
+
+#include <nvgpu/types.h>
+
+struct unit_module;
+struct gk20a;
+
+/** @addtogroup SWUTS-fifo-engine
+ *  @{
+ *
+ * Software Unit Test Specification for fifo/engine
+ */
+
+/**
+ * Test specification for: test_engines_setup_sw
+ *
+ * Description: Branch coverage for nvgpu_channel_setup/cleanup_sw.
+ *
+ * Test Type: Feature based
+ *
+ * Input: None
+ *
+ * Steps:
+ * - Check valid case for nvgpu_channel_setup_sw.
+ * - Check valid case for nvgpu_channel_cleanup_sw.
+ * - Check invalid case for nvgpu_channel_setup_sw.
+ *   - Failure to allocate channel contexts (by using fault injection for
+ *     vzalloc).
+ *
+ * Output: Returns PASS if all branches gave expected results. FAIL otherwise.
+ */
+int test_engine_setup_sw(struct unit_module *m,
+		struct gk20a *g, void *args);
+
+/**
+ * Test specification for: test_engine_init_info
+ *
+ * Description: Branch coverage for nvgpu_engine_init_info
+ *
+ * Test Type: Feature based
+ *
+ * Input: test_fifo_init_support must have run.
+ *
+ * Steps:
+ * - Check valid cases for nvgpu_engine_init_info using gv11b HALs.
+ *   - Check that function returns 0 and that number of engines is > 0.
+ * - Check invalid cases for nvgpu_engine_init_info:
+ *   - g->ops.top.get_device_info is NULL
+ *   - g->ops.top.get_device_info returns failure
+ *   - g->ops.pbdma.find_for_runlist fails to find PBDMA servicing the engine.
+ *   - Check that function returns < 0 and that number of engines is 0.
+ *
+ * Output: Returns PASS if all branches gave expected results. FAIL otherwise.
+ */
+int test_engine_init_info(struct unit_module *m,
+		struct gk20a *g, void *args);
+
+/**
+ * Test specification for: test_engine_ids
+ *
+ * Description: Branch coverage for nvgpu_engine_get_ids,
+ *              nvgpu_engine_check_valid_id and
+ *              nvgpu_engine_get_gr_id
+ *
+ * Test Type: Feature based
+ *
+ * Input: test_fifo_init_support must have run.
+ *
+ * Steps:
+ * - Check nvgpu_engine_check_valid_id returns false for U32_MAX
+ * - Get engine ids for all engine enums in NVGPU_ENGINE_GR to
+ *   NVGPU_ENGINE_INVAL
+ *   - Check that all returned ids are valid  with nvgpu_engine_check_valid_id.
+ *   - Check that nvgpu_engine_get_gr_id is in the returned ids for
+ *     NVGPU_ENGINE_GR
+ *   - Build a mask of CE engines (for other test use)
+ *   - Build a mask of active engines (for other test use)
+ *
+ * Output: Returns PASS if all branches gave expected results. FAIL otherwise.
+ */
+int test_engine_ids(struct unit_module *m,
+		struct gk20a *g, void *args);
+
+/**
+ * Test specification for: test_engine_get_active_eng_info
+ *
+ * Description: Branch coverage for nvgpu_engine_get_active_eng_info
+  *
+ * Test Type: Feature based
+ *
+ * Input: test_engine_ids must have run.
+ *
+ * Steps:
+ * - For each H/W engine id, call nvgpu_engine_get_active_eng_info:
+ *   - Check that info is non NULL for active engines.
+ *   - Check that info is NULL for inactive engines.
+ * - Check that nvgpu_engine_get_active_eng_info returns NULL when g == NULL.
+ * - Check that nvgpu_engine_get_active_eng_info returns NULL when f->max_engines == 0.
+ * - Check that nvgpu_engine_get_active_eng_info returns NULL when f->num_engines == 0.
+ *
+ * Output: Returns PASS if all branches gave expected results. FAIL otherwise.
+ */
+int test_engine_get_active_eng_info(struct unit_module *m,
+		struct gk20a *g, void *args);
+
+/**
+ * Test specification for: test_engine_enum_from_type
+ *
+ * Description: Branch coverage for nvgpu_engine_enum_from_type
+  *
+ * Test Type: Feature based
+ *
+ * Input: test_engine_ids must have run.
+ *
+ * Steps:
+ * - For each HW enum type, call nvgpu_engine_enum_from_type.
+ *   - Check that NVGPU_ENGINE_GR is returned for
+ *     top_device_info_type_enum_graphics_v().
+ *   - Check that NVGPU_ENGINE_ASYNC_CE is returned for
+ *     top_device_info_type_enum_lce_v().
+ *   - Check that NVGPU_ENGINE_INVAL is returned for other values.
+ *
+ * Output: Returns PASS if all branches gave expected results. FAIL otherwise.
+ */
+int test_engine_enum_from_type(struct unit_module *m,
+		struct gk20a *g, void *args);
+
+
+/**
+ * Test specification for: test_engine_interrupt_mask
+ *
+ * Description: Branch coverage for nvgpu_engine_interrupt_mask,
+ *              nvgpu_engine_act_interrupt_mask and
+ *              nvgpu_engine_get_all_ce_reset_mask
+ *
+ * Test Type: Feature based
+ *
+ * Input: test_engine_ids must have run.
+ *
+ * Steps:
+ * - Get interrupt mask for all engines using ngpu_engine_interrupt_mask.
+ *   - Check that engine_intr_mask in non NULL
+ * - For each active engine, get interrupt mask with
+ *   nvgpu_engine_act_interrupt_mask.
+ *   - Check that mask in non NULL
+ *   - Check that mask is contained in engine_intr_mask.
+ *   - Check that engine_intr_mask only contains active engines
+ * - Get CE reset mask using nvgpu_engine_get_all_ce_reset_mask
+ *   - Check that ce_reset_mask == ce_mask (from unit context)
+ *
+ * Output: Returns PASS if all branches gave expected results. FAIL otherwise.
+ */
+int test_engine_interrupt_mask(struct unit_module *m,
+		struct gk20a *g, void *args);
+
+
+
+
+/**
+ * @}
+ */
+
+#endif /* UNIT_NVGPU_ENGINE_H */