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gpu: nvgpu: gp10b: Use T186 POWER DOMAIN macros

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The driver file gp10b/platform_gp10b_tegra.c is compiled for
T186 SOCs and hence use the T186 power domain macros directly
instead of legacy TEGRA_POWERGATE_* macros.

This helps in kernel unification to not define the TEGRA_POWERGATE_*

bug 200257351

Change-Id: I955c5dd11e6deaaf537377beb6e67a58ab7787ab
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/1300524
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Laxman Dewangan
2017-02-07 17:21:03 +05:30
committed by mobile promotions
parent 8264681bb6
commit 27dd1ce475
1 changed files with 5 additions and 5 deletions
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10
drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c
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@@ -16,7 +16,7 @@
#include <linux/of_platform.h>
#include <linux/nvhost.h>
#include <linux/debugfs.h>
#include <linux/tegra-powergate.h>
#include <soc/tegra/tegra_powergate.h>
#include <linux/platform_data/tegra_edp.h>
#include <linux/dma-buf.h>
#include <linux/nvmap.h>
@@ -207,7 +207,7 @@ static bool gp10b_tegra_is_railgated(struct device *dev)
bool ret = false;
if (tegra_bpmp_running())
ret = !tegra_powergate_is_powered(TEGRA_POWERGATE_GPU);
ret = !tegra_powergate_is_powered(TEGRA186_POWER_DOMAIN_GPU);
return ret;
}
@@ -224,13 +224,13 @@ static int gp10b_tegra_railgate(struct device *dev)
0, TEGRA_BWMGR_SET_EMC_FLOOR);
if (tegra_bpmp_running() &&
tegra_powergate_is_powered(TEGRA_POWERGATE_GPU)) {
tegra_powergate_is_powered(TEGRA186_POWER_DOMAIN_GPU)) {
int i;
for (i = 0; i < platform->num_clks; i++) {
if (platform->clk[i])
clk_disable_unprepare(platform->clk[i]);
}
tegra_powergate_partition(TEGRA_POWERGATE_GPU);
tegra_powergate_partition(TEGRA186_POWER_DOMAIN_GPU);
}
return 0;
}
@@ -243,7 +243,7 @@ static int gp10b_tegra_unrailgate(struct device *dev)
if (tegra_bpmp_running()) {
int i;
ret = tegra_unpowergate_partition(TEGRA_POWERGATE_GPU);
ret = tegra_unpowergate_partition(TEGRA186_POWER_DOMAIN_GPU);
for (i = 0; i < platform->num_clks; i++) {
if (platform->clk[i])
clk_prepare_enable(platform->clk[i]);