nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-22 17:36:20 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: fix running condition on fifo isr

Browse Source 
The fifo interrupt path was reading the PBDMA interrupt status
after clearing interrupts and this could lead to a situation in
which the host may have advanced to another channel, leading to
the recovery code resetting the wrong channel.

Bug 200278729
JIRA: EVLR-1036

Change-Id: I392423d1eaa8d23acf88454bf113c015e649e13d
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1326461
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
(cherry picked from commit ab401c7068)
Reviewed-on: http://git-master/r/1327292
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
This commit is contained in:
David Nieto
2017-03-22 16:57:56 -07:00
committed by mobile promotions
parent 42db3e1879
commit 280a628a67
1 changed files with 2 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
View File

@@ -2202,6 +2202,8 @@ static u32 gk20a_fifo_handle_pbdma_intr(struct device *dev,
{
u32 pbdma_intr_0 = gk20a_readl(g, pbdma_intr_0_r(pbdma_id));
u32 pbdma_intr_1 = gk20a_readl(g, pbdma_intr_1_r(pbdma_id));
u32 status = gk20a_readl(g, fifo_pbdma_status_r(pbdma_id));
u32 handled = 0;
u32 error_notifier = NVGPU_CHANNEL_PBDMA_ERROR;
bool reset = false;
@@ -2287,7 +2289,6 @@ static u32 gk20a_fifo_handle_pbdma_intr(struct device *dev,
if (reset) {
/* Remove the channel from runlist */
u32 status = gk20a_readl(g, fifo_pbdma_status_r(pbdma_id));
u32 id = fifo_pbdma_status_id_v(status);
if (fifo_pbdma_status_id_type_v(status)
== fifo_pbdma_status_id_type_chid_v()) {