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gpu: nvgpu: Fix leaf and top interrupt disabling logic

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There are 2 issues here:
1. top_en register is being masked for each leaf level
interrupt disable operation. top_en bit should be disabled
as part of top level stall operation only.
2. Wrong mask is being calculated to disable the leaf_en bits
for a unit which inturn affects the entire subtree.
Subtree_mask_restore for a subtree stores the last state
of interrupts that are enabled. As part of disable operation,
we only need to update subtree_mask_restore and not reupdate
subtree_mask for that subtree. Same logic applies to enable
operation.

Renamed the apis to better reflect their operation. The
interrupt disabling is done at unit level and not subtree level.

Bug 3712884

Change-Id: Id840c77f612021a303cfe0e8dca69386bc570273
Signed-off-by: Kishan <kpalankar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2752541
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-by: Deepak Goyal <dgoyal@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Kishan
2022-07-28 12:17:44 +00:00
committed by mobile promotions
parent b83d4ed668
commit 282be07995
1 changed files with 9 additions and 17 deletions
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24
drivers/gpu/nvgpu/hal/mc/mc_intr_ga10b_fusa.c
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@@ -111,21 +111,22 @@ static void ga10b_intr_subtree_clear(struct gk20a *g, u32 subtree,
subtree, subtree_mask);
}
static void ga10b_intr_subtree_enable(struct gk20a *g, u32 subtree,
static void ga10b_intr_unit_enable(struct gk20a *g, u32 subtree,
u64 subtree_mask)
{
/**
* Enable interrupts in Top and Leaf registers for the subtree.
* Enable interrupts in Top & Leaf registers for the subtree.
* top bit 0 -> subtree 0 -> leaf0, leaf1 -> leaf 0, 1
* top bit 1 -> subtree 1 -> leaf0, leaf1 -> leaf 2, 3
* top bit 2 -> subtree 2 -> leaf0, leaf1 -> leaf 4, 5
* top bit 3 -> subtree 3 -> leaf0, leaf1 -> leaf 6, 7
*/
//TODO top_en manipulation needs to be decoupled from leaf_en enablement
//process.
nvgpu_func_writel(g,
func_priv_cpu_intr_top_en_set_r(
HOST2SOC_SUBTREE_TO_TOP_IDX(subtree)),
BIT32(HOST2SOC_SUBTREE_TO_TOP_BIT(subtree)));
nvgpu_func_writel(g,
func_priv_cpu_intr_leaf_en_set_r(
HOST2SOC_SUBTREE_TO_LEAF0(subtree)),
@@ -139,21 +140,16 @@ static void ga10b_intr_subtree_enable(struct gk20a *g, u32 subtree,
subtree, subtree_mask);
}
static void ga10b_intr_subtree_disable(struct gk20a *g, u32 subtree,
static void ga10b_intr_unit_disable(struct gk20a *g, u32 subtree,
u64 subtree_mask)
{
/**
* Disable interrupts in Top and Leaf registers for the subtree.
* Disable unit specific Leaf interrupt registers for the subtree.
* top bit 0 -> subtree 0 -> leaf0, leaf1 -> leaf 0, 1
* top bit 1 -> subtree 1 -> leaf0, leaf1 -> leaf 2, 3
* top bit 2 -> subtree 2 -> leaf0, leaf1 -> leaf 4, 5
* top bit 3 -> subtree 3 -> leaf0, leaf1 -> leaf 6, 7
*/
nvgpu_func_writel(g,
func_priv_cpu_intr_top_en_clear_r(
HOST2SOC_SUBTREE_TO_TOP_IDX(subtree)),
BIT32(HOST2SOC_SUBTREE_TO_TOP_BIT(subtree)));
nvgpu_func_writel(g,
func_priv_cpu_intr_leaf_en_clear_r(
HOST2SOC_SUBTREE_TO_LEAF0(subtree)),
@@ -173,15 +169,11 @@ static void ga10b_intr_config(struct gk20a *g, bool enable, u32 subtree,
if (enable) {
g->mc.subtree_mask_restore[subtree] |=
subtree_mask;
subtree_mask = g->mc.subtree_mask_restore[subtree];
ga10b_intr_subtree_enable(g, subtree, subtree_mask);
ga10b_intr_unit_enable(g, subtree, subtree_mask);
} else {
g->mc.subtree_mask_restore[subtree] &=
~(subtree_mask);
subtree_mask = g->mc.subtree_mask_restore[subtree];
ga10b_intr_subtree_disable(g, subtree, subtree_mask);
ga10b_intr_unit_disable(g, subtree, subtree_mask);
}
}