gpu: nvgpu: unit: enable engine tests on target

Add the following tests to target makefile:
- engine
- engine/gm20b
- engine/gp10b
- engine/gv100
- engine/gv11b

Fix build issues for unit tests on QNX safety.
Update export files to fix link issues.
Update list of required tests in JSON file.

Jira NVGPU-3695

Change-Id: I373c6c8575ed4cbf6c5597502f2ca6ec2f078ca4
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2253506
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

Makefile.umbrella.tmk

@@ -74,6 +74,11 @@ NV_REPOSITORY_COMPONENTS += userspace/units/fifo/channel
 NV_REPOSITORY_COMPONENTS += userspace/units/fifo/channel/gk20a
 NV_REPOSITORY_COMPONENTS += userspace/units/fifo/channel/gm20b
 NV_REPOSITORY_COMPONENTS += userspace/units/fifo/channel/gv11b
+NV_REPOSITORY_COMPONENTS += userspace/units/fifo/engine
+NV_REPOSITORY_COMPONENTS += userspace/units/fifo/engine/gm20b
+NV_REPOSITORY_COMPONENTS += userspace/units/fifo/engine/gp10b
+NV_REPOSITORY_COMPONENTS += userspace/units/fifo/engine/gv100
+NV_REPOSITORY_COMPONENTS += userspace/units/fifo/engine/gv11b
 NV_REPOSITORY_COMPONENTS += userspace/units/fifo/pbdma
 NV_REPOSITORY_COMPONENTS += userspace/units/fifo/runlist
 NV_REPOSITORY_COMPONENTS += userspace/units/fifo/runlist/gk20a

drivers/gpu/nvgpu/libnvgpu-drv_safe.export

@@ -177,6 +177,12 @@ nvgpu_cg_elcg_enable_no_wait
 nvgpu_cg_elcg_disable_no_wait
 nvgpu_current_pid
 nvgpu_current_tid
+nvgpu_engine_cleanup_sw
+nvgpu_engine_get_active_eng_info
+nvgpu_engine_get_ids
+nvgpu_engine_get_gr_id
+nvgpu_engine_init_info
+nvgpu_engine_setup_sw
 nvgpu_gr_alloc
 nvgpu_gr_free
 nvgpu_gr_init
@@ -226,6 +232,7 @@ nvgpu_gr_config_set_sm_info_sm_index
 nvgpu_gr_config_get_sm_info_sm_index
 nvgpu_gr_config_set_gpc_tpc_mask
 nvgpu_gr_config_get_gpc_tpc_mask
+nvgpu_gr_engine_interrupt_mask
 nvgpu_gr_obj_ctx_is_golden_image_ready
 nvgpu_gr_ctx_get_tsgid
 nvgpu_gr_get_config_ptr
@@ -239,6 +246,7 @@ nvgpu_ltc_get_slices_per_ltc
 nvgpu_ltc_remove_support
 nvgpu_ltc_sync_enabled
 nvgpu_can_busy
+nvgpu_ce_engine_interrupt_mask
 nvgpu_channel_alloc_inst
 nvgpu_channel_cleanup_sw
 nvgpu_channel_close
@@ -278,6 +286,10 @@ nvgpu_dma_free
 nvgpu_dma_unmap_free
 nvgpu_ecc_counter_init_per_lts
 nvgpu_ecc_init_support
+nvgpu_engine_act_interrupt_mask
+nvgpu_engine_check_valid_id
+nvgpu_engine_enum_from_type
+nvgpu_engine_get_all_ce_reset_mask
 nvgpu_engine_get_fast_ce_runlist_id
 nvgpu_engine_get_gr_runlist_id
 nvgpu_engine_is_valid_runlist_id

userspace/required_tests.json

@@ -1391,6 +1391,120 @@
         "unit": "nvgpu_channel_gv11b",
         "test_level": 0
     },
+    {
+        "test": "test_engine_enum_from_type",
+        "case": "enum_from_type",
+        "unit": "nvgpu_engine",
+        "test_level": 0
+    },
+    {
+        "test": "test_engine_get_active_eng_info",
+        "case": "get_active_eng_info",
+        "unit": "nvgpu_engine",
+        "test_level": 0
+    },
+    {
+        "test": "test_engine_ids",
+        "case": "ids",
+        "unit": "nvgpu_engine",
+        "test_level": 0
+    },
+    {
+        "test": "test_engine_init_info",
+        "case": "init_info",
+        "unit": "nvgpu_engine",
+        "test_level": 0
+    },
+    {
+        "test": "test_fifo_init_support",
+        "case": "init_support",
+        "unit": "nvgpu_engine",
+        "test_level": 0
+    },
+    {
+        "test": "test_engine_interrupt_mask",
+        "case": "interrupt_mask",
+        "unit": "nvgpu_engine",
+        "test_level": 0
+    },
+    {
+        "test": "test_fifo_remove_support",
+        "case": "remove_support",
+        "unit": "nvgpu_engine",
+        "test_level": 0
+    },
+    {
+        "test": "test_engine_setup_sw",
+        "case": "setup_sw",
+        "unit": "nvgpu_engine",
+        "test_level": 0
+    },
+    {
+        "test": "test_fifo_init_support",
+        "case": "init_support",
+        "unit": "nvgpu_engine_gm20b",
+        "test_level": 0
+    },
+    {
+        "test": "test_gm20b_read_engine_status_info",
+        "case": "read_engine_status_info",
+        "unit": "nvgpu_engine_gm20b",
+        "test_level": 0
+    },
+    {
+        "test": "test_fifo_remove_support",
+        "case": "remove_support",
+        "unit": "nvgpu_engine_gm20b",
+        "test_level": 0
+    },
+    {
+        "test": "test_gp10b_engine_init_ce_info",
+        "case": "engine_init_ce_info",
+        "unit": "nvgpu_engine_gp10b",
+        "test_level": 0
+    },
+    {
+        "test": "test_fifo_init_support",
+        "case": "init_support",
+        "unit": "nvgpu_engine_gp10b",
+        "test_level": 0
+    },
+    {
+        "test": "test_fifo_remove_support",
+        "case": "remove_support",
+        "unit": "nvgpu_engine_gp10b",
+        "test_level": 0
+    },
+    {
+        "test": "test_gv100_dump_engine_status",
+        "case": "dump_engine_status_info",
+        "unit": "nvgpu_engine_gv100",
+        "test_level": 0
+    },
+    {
+        "test": "test_fifo_init_support",
+        "case": "init_support",
+        "unit": "nvgpu_engine_gv100",
+        "test_level": 0
+    },
+    {
+        "test": "test_gv100_read_engine_status_info",
+        "case": "read_engine_status_info",
+        "unit": "nvgpu_engine_gv100",
+        "test_level": 0
+    },
+    {
+        "test": "test_fifo_remove_support",
+        "case": "remove_support",
+        "unit": "nvgpu_engine_gv100",
+        "test_level": 0
+    },
+    {
+        "test": "test_gv11b_is_fault_engine_subid_gpc",
+        "case": "is_fault_engine_subid_gpc",
+        "unit": "nvgpu_engine_gv11b",
+        "test_level": 0
+    },
     {
         "test": "test_gr_config_count",
         "case": "config_check_init",

userspace/units/fifo/engine/nvgpu-engine.c

@@ -95,8 +95,8 @@ int test_engine_setup_sw(struct unit_module *m,
 {
 	struct gpu_ops gops = g->ops;
 	struct nvgpu_fifo *f = &g->fifo;
-	struct nvgpu_posix_fault_inj *kmem_fi;
+	struct nvgpu_posix_fault_inj *kmem_fi = NULL;
-	u32 branches;
+	u32 branches = 0;
 	int ret = UNIT_FAIL;
 	int err;
 	u32 fail = F_ENGINE_SETUP_SW_ENGINE_INFO_ENOMEM |
@@ -312,7 +312,7 @@ int test_engine_get_active_eng_info(struct unit_module *m,
 	int ret = UNIT_FAIL;
 	u32 engine_id;
 	struct nvgpu_engine_info *info;
-	u32 eng_mask;
+	u32 eng_mask = 0;
 	struct nvgpu_fifo *f = &g->fifo;
 
 	for (engine_id = 0; engine_id < f->max_engines; engine_id++) {