From 28ccd63f695f4461e837a3823f1b54340359656b Mon Sep 17 00:00:00 2001 From: Thomas Fleury Date: Fri, 20 Mar 2020 11:06:40 -0400 Subject: [PATCH] gpu: nvgpu: enable CONFIG_NVGPU_LS_PMU for safety Enable CONFIG_NVGPU_LS_PMU for dGPU safety build. Add missing #ifdefs for CONFIG_NVGPU_POWER_PG and CONFIG_NVGPU_CLK_ARB which are not defined for safety build. Moved gm20b_mc_is_enabled to fusa code. NVGPU_UNIT_PWR is only defined when CONFIG_NVGPU_HAL_NON_FUSA is defined. Added #ifdefs to compile out gk20a_pmu functions that are using it. Jira NVGPU-4661 Change-Id: Ieb552f9374bad6f3dad777322f118931e0bc94ec Signed-off-by: Thomas Fleury Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2317085 Reviewed-by: automaticguardword Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-cert Reviewed-by: Deepak Nibade Reviewed-by: mobile promotions Tested-by: mobile promotions GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/Makefile.shared.configs | 3 +++ drivers/gpu/nvgpu/Makefile.sources | 18 ++++++++++------- drivers/gpu/nvgpu/common/gr/obj_ctx.c | 4 ++-- .../gpu/nvgpu/common/pmu/clk/clk_vf_point.c | 2 ++ drivers/gpu/nvgpu/common/pmu/perf/perf.c | 2 ++ drivers/gpu/nvgpu/common/pmu/pmu_rtos_init.c | 20 ++++++++++++++++--- drivers/gpu/nvgpu/hal/mc/mc_gm20b.c | 8 -------- drivers/gpu/nvgpu/hal/mc/mc_gm20b_fusa.c | 9 +++++++++ drivers/gpu/nvgpu/hal/pmu/pmu_gk20a.c | 4 +++- 9 files changed, 49 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/nvgpu/Makefile.shared.configs b/drivers/gpu/nvgpu/Makefile.shared.configs index d528ec667..791bf1951 100644 --- a/drivers/gpu/nvgpu/Makefile.shared.configs +++ b/drivers/gpu/nvgpu/Makefile.shared.configs @@ -117,6 +117,9 @@ NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_SM_DIVERSITY CONFIG_NVGPU_USE_3LSS_ERR_INJECTION := 1 NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_USE_3LSS_ERR_INJECTION + +CONFIG_NVGPU_LS_PMU := 1 +NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_LS_PMU endif endif diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources index 232766bdb..21f9218df 100644 --- a/drivers/gpu/nvgpu/Makefile.sources +++ b/drivers/gpu/nvgpu/Makefile.sources @@ -326,7 +326,8 @@ srcs += hal/gr/falcon/gr_falcon_gm20b.c \ hal/fb/fb_gp106.c \ hal/falcon/falcon_gk20a.c \ hal/bus/bus_gk20a.c \ - hal/gr/ctxsw_prog/ctxsw_prog_gm20b.c + hal/gr/ctxsw_prog/ctxsw_prog_gm20b.c \ + hal/pmu/pmu_gv11b.c endif endif @@ -475,12 +476,6 @@ srcs += \ common/pmu/perfmon/pmu_perfmon.c \ common/pmu/perfmon/pmu_perfmon_sw_gm20b.c \ common/pmu/perfmon/pmu_perfmon_sw_gv11b.c \ - common/pmu/pg/pg_sw_gm20b.c \ - common/pmu/pg/pg_sw_gp10b.c \ - common/pmu/pg/pg_sw_gp106.c \ - common/pmu/pg/pg_sw_gv11b.c \ - common/pmu/pg/pmu_pg.c \ - common/pmu/pg/pmu_aelpg.c \ common/pmu/pmgr/pmgr.c \ common/pmu/pmgr/pmgrpmu.c \ common/pmu/pmgr/pwrdev.c \ @@ -504,6 +499,15 @@ srcs += \ hal/pmu/pmu_gp10b.c \ hal/pmu/pmu_tu104.c +ifeq ($(CONFIG_NVGPU_POWER_PG),1) +srcs += common/pmu/pg/pg_sw_gm20b.c \ + common/pmu/pg/pg_sw_gp10b.c \ + common/pmu/pg/pg_sw_gp106.c \ + common/pmu/pg/pg_sw_gv11b.c \ + common/pmu/pg/pmu_pg.c \ + common/pmu/pg/pmu_aelpg.c +endif + ifeq ($(CONFIG_NVGPU_CLK_ARB),1) srcs += common/clk_arb/clk_arb_gv100.c endif diff --git a/drivers/gpu/nvgpu/common/gr/obj_ctx.c b/drivers/gpu/nvgpu/common/gr/obj_ctx.c index 6d7e3d922..055180a1f 100644 --- a/drivers/gpu/nvgpu/common/gr/obj_ctx.c +++ b/drivers/gpu/nvgpu/common/gr/obj_ctx.c @@ -716,7 +716,7 @@ int nvgpu_gr_obj_ctx_alloc_golden_ctx_image(struct gk20a *g, } golden_image->ready = true; -#ifdef CONFIG_NVGPU_LS_PMU +#ifdef CONFIG_NVGPU_POWER_PG nvgpu_pmu_set_golden_image_initialized(g, true); #endif g->ops.gr.falcon.set_current_ctx_invalid(g); @@ -923,7 +923,7 @@ void nvgpu_gr_obj_ctx_deinit(struct gk20a *g, golden_image->local_golden_image); golden_image->local_golden_image = NULL; } -#ifdef CONFIG_NVGPU_LS_PMU +#ifdef CONFIG_NVGPU_POWER_PG nvgpu_pmu_set_golden_image_initialized(g, false); #endif golden_image->ready = false; diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk_vf_point.c b/drivers/gpu/nvgpu/common/pmu/clk/clk_vf_point.c index 0c6510735..9d81ada6f 100644 --- a/drivers/gpu/nvgpu/common/pmu/clk/clk_vf_point.c +++ b/drivers/gpu/nvgpu/common/pmu/clk/clk_vf_point.c @@ -494,7 +494,9 @@ int clk_vf_point_init_pmupstate(struct gk20a *g) return -ENOMEM; } +#ifdef CONFIG_NVGPU_CLK_ARB g->pmu->clk_pmu->nvgpu_clk_vf_point_cache = nvgpu_clk_vf_point_cache; +#endif return 0; } diff --git a/drivers/gpu/nvgpu/common/pmu/perf/perf.c b/drivers/gpu/nvgpu/common/pmu/perf/perf.c index 58d347617..b8fd5330a 100644 --- a/drivers/gpu/nvgpu/common/pmu/perf/perf.c +++ b/drivers/gpu/nvgpu/common/pmu/perf/perf.c @@ -51,7 +51,9 @@ static int pmu_set_boot_clk_runcb_fn(void *arg) } vfe_init->state_change = false; +#ifdef CONFIG_NVGPU_CLK_ARB nvgpu_clk_arb_schedule_vf_table_update(g); +#endif } return 0; diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_rtos_init.c b/drivers/gpu/nvgpu/common/pmu/pmu_rtos_init.c index 763d20068..b7909e65c 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_rtos_init.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_rtos_init.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -31,17 +31,19 @@ #include #include -#include #include #include #include #include #include -#include #include #include #include +#ifdef CONFIG_NVGPU_POWER_PG +#include +#endif + #ifdef CONFIG_NVGPU_DGPU #include #endif @@ -58,9 +60,11 @@ int nvgpu_pmu_lock_acquire(struct gk20a *g, struct nvgpu_pmu *pmu, return 0; } +#ifdef CONFIG_NVGPU_POWER_PG if (!pmu->pg->initialized) { return -EINVAL; } +#endif return nvgpu_pmu_mutex_acquire(g, pmu->mutexes, id, token); } @@ -76,9 +80,11 @@ int nvgpu_pmu_lock_release(struct gk20a *g, struct nvgpu_pmu *pmu, return 0; } +#ifdef CONFIG_PMU_POWER_PG if (!pmu->pg->initialized) { return -EINVAL; } +#endif return nvgpu_pmu_mutex_release(g, pmu->mutexes, id, token); } @@ -88,9 +94,11 @@ int nvgpu_pmu_destroy(struct gk20a *g, struct nvgpu_pmu *pmu) { nvgpu_log_fn(g, " "); +#ifdef CONFIG_NVGPU_POWER_PG if (g->can_elpg) { nvgpu_pmu_pg_destroy(g, pmu, pmu->pg); } +#endif nvgpu_pmu_queues_free(g, &pmu->queues); @@ -144,7 +152,9 @@ static void remove_pmu_support(struct nvgpu_pmu *pmu) nvgpu_pmu_debug_deinit(g, pmu); nvgpu_pmu_lsfm_deinit(g, pmu, pmu->lsfm); +#ifdef CONFIG_PMU_POWER_PG nvgpu_pmu_pg_deinit(g, pmu, pmu->pg); +#endif nvgpu_pmu_sequences_deinit(g, pmu, pmu->sequences); nvgpu_pmu_mutexe_deinit(g, pmu, pmu->mutexes); nvgpu_pmu_fw_deinit(g, pmu, pmu->fw); @@ -163,12 +173,14 @@ static int pmu_sw_setup(struct gk20a *g, struct nvgpu_pmu *pmu ) /* set default value to sequences */ nvgpu_pmu_sequences_sw_setup(g, pmu, pmu->sequences); +#ifdef CONFIG_NVGPU_POWER_PG if (g->can_elpg) { err = nvgpu_pmu_pg_sw_setup(g, pmu, pmu->pg); if (err != 0){ goto exit; } } +#endif if (pmu->sw_ready) { nvgpu_log_fn(g, "skip PMU-RTOS shared buffer realloc"); @@ -295,12 +307,14 @@ int nvgpu_pmu_rtos_early_init(struct gk20a *g, struct nvgpu_pmu *pmu) goto init_failed; } +#ifdef CONFIG_NVGPU_POWER_PG if (g->can_elpg) { err = nvgpu_pmu_pg_init(g, pmu, &pmu->pg); if (err != 0) { goto init_failed; } } +#endif err = nvgpu_pmu_lsfm_init(g, &pmu->lsfm); if (err != 0) { diff --git a/drivers/gpu/nvgpu/hal/mc/mc_gm20b.c b/drivers/gpu/nvgpu/hal/mc/mc_gm20b.c index d1925b420..aff012922 100644 --- a/drivers/gpu/nvgpu/hal/mc/mc_gm20b.c +++ b/drivers/gpu/nvgpu/hal/mc/mc_gm20b.c @@ -300,11 +300,3 @@ bool gm20b_mc_is_mmu_fault_pending(struct gk20a *g) return g->ops.fifo.is_mmu_fault_pending(g); } -#ifdef CONFIG_NVGPU_LS_PMU -bool gm20b_mc_is_enabled(struct gk20a *g, enum nvgpu_unit unit) -{ - u32 mask = g->ops.mc.reset_mask(g, unit); - - return (nvgpu_readl(g, mc_enable_r()) & mask) != 0U; -} -#endif diff --git a/drivers/gpu/nvgpu/hal/mc/mc_gm20b_fusa.c b/drivers/gpu/nvgpu/hal/mc/mc_gm20b_fusa.c index 9789cb9cd..413a73792 100644 --- a/drivers/gpu/nvgpu/hal/mc/mc_gm20b_fusa.c +++ b/drivers/gpu/nvgpu/hal/mc/mc_gm20b_fusa.c @@ -164,3 +164,12 @@ u32 gm20b_mc_reset_mask(struct gk20a *g, enum nvgpu_unit unit) return mask; } + +#ifdef CONFIG_NVGPU_LS_PMU +bool gm20b_mc_is_enabled(struct gk20a *g, enum nvgpu_unit unit) +{ + u32 mask = g->ops.mc.reset_mask(g, unit); + + return (nvgpu_readl(g, mc_enable_r()) & mask) != 0U; +} +#endif \ No newline at end of file diff --git a/drivers/gpu/nvgpu/hal/pmu/pmu_gk20a.c b/drivers/gpu/nvgpu/hal/pmu/pmu_gk20a.c index 8471fa9d1..8c1f4757d 100644 --- a/drivers/gpu/nvgpu/hal/pmu/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/hal/pmu/pmu_gk20a.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2011-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -688,6 +688,7 @@ int gk20a_pmu_ns_bootstrap(struct gk20a *g, struct nvgpu_pmu *pmu, return err; } +#ifdef CONFIG_NVGPU_HAL_NON_FUSA bool gk20a_pmu_is_engine_in_reset(struct gk20a *g) { bool status = false; @@ -707,6 +708,7 @@ void gk20a_pmu_engine_reset(struct gk20a *g, bool do_reset) g->ops.mc.disable(g, reset_mask); } } +#endif void gk20a_write_dmatrfbase(struct gk20a *g, u32 addr) {