diff --git a/drivers/gpu/nvgpu/hal/fifo/tsg_gv11b_fusa.c b/drivers/gpu/nvgpu/hal/fifo/tsg_gv11b_fusa.c index 943b4277a..760cef6bb 100644 --- a/drivers/gpu/nvgpu/hal/fifo/tsg_gv11b_fusa.c +++ b/drivers/gpu/nvgpu/hal/fifo/tsg_gv11b_fusa.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2021, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -111,7 +111,6 @@ int gv11b_tsg_init_eng_method_buffers(struct gk20a *g, struct nvgpu_tsg *tsg) int err = 0; int i; unsigned int runque, buffer_size; - u32 page_size = U32(NVGPU_CPU_PAGE_SIZE); unsigned int num_pbdma = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_PBDMA); if (tsg->eng_method_buffers != NULL) { @@ -122,7 +121,7 @@ int gv11b_tsg_init_eng_method_buffers(struct gk20a *g, struct nvgpu_tsg *tsg) buffer_size = nvgpu_safe_add_u32(nvgpu_safe_mult_u32((9U + 1U + 3U), g->ops.ce.get_num_pce(g)), 2U); buffer_size = nvgpu_safe_mult_u32((27U * 5U), buffer_size); - buffer_size = round_up(buffer_size, page_size); + buffer_size = PAGE_ALIGN(buffer_size); nvgpu_log_info(g, "method buffer size in bytes %d", buffer_size); tsg->eng_method_buffers = nvgpu_kzalloc(g, diff --git a/drivers/gpu/nvgpu/include/nvgpu/posix/utils.h b/drivers/gpu/nvgpu/include/nvgpu/posix/utils.h index 02f73e3b8..7c2da7c12 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/posix/utils.h +++ b/drivers/gpu/nvgpu/include/nvgpu/posix/utils.h @@ -216,6 +216,7 @@ */ #define round_mask(x, y) ((__typeof__(x))((y) - 1U)) +#ifdef CONFIG_NVGPU_NON_FUSA /** * @brief Round up the value of its argument \a x. * @@ -229,6 +230,7 @@ * @return Rounded up value of \a x. */ #define round_up(x, y) ((((x) - 1U) | round_mask(x, y)) + 1U) +#endif /** * @brief Round down the value of its argument \a x. diff --git a/drivers/gpu/nvgpu/os/posix/bitmap.c b/drivers/gpu/nvgpu/os/posix/bitmap.c index 2423b4a79..68e56029e 100644 --- a/drivers/gpu/nvgpu/os/posix/bitmap.c +++ b/drivers/gpu/nvgpu/os/posix/bitmap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -111,8 +111,6 @@ static unsigned long nvgpu_posix_find_next_bit(const unsigned long *address, idx = start / BITS_PER_LONG; w = (base_addr[idx] ^ invert_mask) & start_mask; - start = round_up(start, BITS_PER_LONG); - idx_max = (n - 1UL) / BITS_PER_LONG; /* @@ -125,8 +123,6 @@ static unsigned long nvgpu_posix_find_next_bit(const unsigned long *address, return n; } - start = nvgpu_safe_add_u64(start, BITS_PER_LONG); - w = base_addr[idx] ^ invert_mask; } diff --git a/userspace/units/posix/utils/posix-utils.c b/userspace/units/posix/utils/posix-utils.c index 785e38c76..e7a063048 100644 --- a/userspace/units/posix/utils/posix-utils.c +++ b/userspace/units/posix/utils/posix-utils.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -460,7 +460,7 @@ int test_round_macros(struct unit_module *m, "round_mask failure %d\n", result); } } - +#ifdef CONFIG_NVGPU_NON_FUSA result = ROUND_BY_VALUE; for (i = 0; i < ROUND_BY_VALUE; i++) { test1 = (ROUND_DOWN_RESULT + 1U) + i; @@ -468,6 +468,7 @@ int test_round_macros(struct unit_module *m, unit_return_fail(m, "round_up failure %d %d\n", test1, i); } } +#endif result = ROUND_BY_VALUE; for (i = 0; i < ROUND_BY_VALUE; i++) {