diff --git a/drivers/gpu/nvgpu/hal/fifo/channel_gv11b_fusa.c b/drivers/gpu/nvgpu/hal/fifo/channel_gv11b_fusa.c index 44fdc6516..d5854e6af 100644 --- a/drivers/gpu/nvgpu/hal/fifo/channel_gv11b_fusa.c +++ b/drivers/gpu/nvgpu/hal/fifo/channel_gv11b_fusa.c @@ -39,11 +39,11 @@ void gv11b_channel_unbind(struct nvgpu_channel *ch) nvgpu_log_fn(g, " "); if (nvgpu_atomic_cmpxchg(&ch->bound, 1, 0) != 0) { - gk20a_writel(g, ccsr_channel_inst_r(ch->chid), + nvgpu_writel(g, ccsr_channel_inst_r(ch->chid), ccsr_channel_inst_ptr_f(0U) | ccsr_channel_inst_bind_false_f()); - gk20a_writel(g, ccsr_channel_r(ch->chid), + nvgpu_writel(g, ccsr_channel_r(ch->chid), ccsr_channel_enable_clr_true_f() | ccsr_channel_pbdma_faulted_reset_f() | ccsr_channel_eng_faulted_reset_f()); @@ -58,7 +58,7 @@ u32 gv11b_channel_count(struct gk20a *g) void gv11b_channel_read_state(struct gk20a *g, struct nvgpu_channel *ch, struct nvgpu_channel_hw_state *state) { - u32 reg = gk20a_readl(g, ccsr_channel_r(ch->chid)); + u32 reg = nvgpu_readl(g, ccsr_channel_r(ch->chid)); gk20a_channel_read_state(g, ch, state); @@ -69,7 +69,7 @@ void gv11b_channel_read_state(struct gk20a *g, struct nvgpu_channel *ch, void gv11b_channel_reset_faulted(struct gk20a *g, struct nvgpu_channel *ch, bool eng, bool pbdma) { - u32 reg = gk20a_readl(g, ccsr_channel_r(ch->chid)); + u32 reg = nvgpu_readl(g, ccsr_channel_r(ch->chid)); if (eng) { reg |= ccsr_channel_eng_faulted_reset_f(); @@ -78,7 +78,7 @@ void gv11b_channel_reset_faulted(struct gk20a *g, struct nvgpu_channel *ch, reg |= ccsr_channel_pbdma_faulted_reset_f(); } - gk20a_writel(g, ccsr_channel_r(ch->chid), reg); + nvgpu_writel(g, ccsr_channel_r(ch->chid), reg); } void gv11b_channel_debug_dump(struct gk20a *g, diff --git a/userspace/Makefile.sources b/userspace/Makefile.sources index 2af38bf85..4376e598d 100644 --- a/userspace/Makefile.sources +++ b/userspace/Makefile.sources @@ -76,6 +76,7 @@ UNITS := \ $(UNIT_SRC)/fifo/channel \ $(UNIT_SRC)/fifo/channel/gk20a \ $(UNIT_SRC)/fifo/channel/gm20b \ + $(UNIT_SRC)/fifo/channel/gv11b \ $(UNIT_SRC)/fifo/runlist \ $(UNIT_SRC)/fifo/tsg \ $(UNIT_SRC)/fifo/tsg/gv11b \ diff --git a/userspace/SWUTS.sources b/userspace/SWUTS.sources index 3a8a9742b..024e16171 100644 --- a/userspace/SWUTS.sources +++ b/userspace/SWUTS.sources @@ -10,6 +10,7 @@ INPUT += ../../../userspace/units/fifo/nvgpu-fifo.h INPUT += ../../../userspace/units/fifo/channel/nvgpu-channel.h INPUT += ../../../userspace/units/fifo/channel/nvgpu-channel-gk20a.h INPUT += ../../../userspace/units/fifo/channel/nvgpu-channel-gm20b.h +INPUT += ../../../userspace/units/fifo/channel/nvgpu-channel-gv11b.h INPUT += ../../../userspace/units/fifo/runlist/nvgpu-runlist.h INPUT += ../../../userspace/units/fifo/tsg/nvgpu-tsg.h INPUT += ../../../userspace/units/fifo/tsg/gv11b/nvgpu-tsg-gv11b.h diff --git a/userspace/units/fifo/channel/gv11b/Makefile b/userspace/units/fifo/channel/gv11b/Makefile new file mode 100644 index 000000000..4564423b3 --- /dev/null +++ b/userspace/units/fifo/channel/gv11b/Makefile @@ -0,0 +1,32 @@ +# Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. + +.SUFFIXES: + +OBJS = nvgpu-channel-gv11b.o +MODULE = nvgpu-channel-gv11b + +LIB_PATHS += -lnvgpu-fifo +include ../../../Makefile.units + +lib$(MODULE).so: fifo + +fifo: + $(MAKE) -C ../.. diff --git a/userspace/units/fifo/channel/gv11b/Makefile.interface.tmk b/userspace/units/fifo/channel/gv11b/Makefile.interface.tmk new file mode 100644 index 000000000..53edba308 --- /dev/null +++ b/userspace/units/fifo/channel/gv11b/Makefile.interface.tmk @@ -0,0 +1,35 @@ +################################### tell Emacs this is a -*- makefile-gmake -*- +# +# Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. +# +# tmake for SW Mobile component makefile +# +############################################################################### + +NVGPU_UNIT_NAME=nvgpu-channel-gv11b + +include $(NV_SOURCE)/kernel/nvgpu/userspace/units/Makefile.units.common.interface.tmk + +# Local Variables: +# indent-tabs-mode: t +# tab-width: 8 +# End: +# vi: set tabstop=8 noexpandtab: diff --git a/userspace/units/fifo/channel/gv11b/Makefile.tmk b/userspace/units/fifo/channel/gv11b/Makefile.tmk new file mode 100644 index 000000000..e5ea41a66 --- /dev/null +++ b/userspace/units/fifo/channel/gv11b/Makefile.tmk @@ -0,0 +1,40 @@ +################################### tell Emacs this is a -*- makefile-gmake -*- +# +# Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. +# +# tmake for SW Mobile component makefile +# +############################################################################### + +NVGPU_UNIT_NAME = nvgpu-channel-gv11b +NVGPU_UNIT_SRCS = nvgpu-channel-gv11b.c + +NVGPU_UNIT_INTERFACE_DIRS := \ + $(NV_SOURCE)/kernel/nvgpu/userspace/units/fifo \ + $(NV_SOURCE)/kernel/nvgpu/drivers/gpu/nvgpu + +include $(NV_SOURCE)/kernel/nvgpu/userspace/units/Makefile.units.common.tmk + +# Local Variables: +# indent-tabs-mode: t +# tab-width: 8 +# End: +# vi: set tabstop=8 noexpandtab: diff --git a/userspace/units/fifo/channel/gv11b/nvgpu-channel-gv11b.c b/userspace/units/fifo/channel/gv11b/nvgpu-channel-gv11b.c new file mode 100644 index 000000000..cef5ad8ad --- /dev/null +++ b/userspace/units/fifo/channel/gv11b/nvgpu-channel-gv11b.c @@ -0,0 +1,320 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "hal/fifo/channel_gk20a.h" +#include "hal/fifo/channel_gm20b.h" +#include "hal/fifo/channel_gv11b.h" + +#include + +#include "../../nvgpu-fifo.h" +#include "nvgpu-channel-gv11b.h" + +#ifdef CHANNEL_GV11B_UNIT_DEBUG +#undef unit_verbose +#define unit_verbose unit_info +#else +#define unit_verbose(unit, msg, ...) \ + do { \ + if (0) { \ + unit_info(unit, msg, ##__VA_ARGS__); \ + } \ + } while (0) +#endif + +#define assert(cond) unit_assert(cond, goto done) + +#define branches_str test_fifo_flags_str +#define pruned test_fifo_subtest_pruned + +struct unit_ctx { + struct unit_module *m; + int count; + int err; + size_t size; +}; + +int test_gv11b_channel_unbind(struct unit_module *m, + struct gk20a *g, void *args) +{ + bool privileged = false; + u32 runlist_id = NVGPU_INVALID_RUNLIST_ID; + struct nvgpu_channel *ch; + int ret = UNIT_FAIL; + + ch = nvgpu_channel_open_new(g, runlist_id, + privileged, getpid(), getpid()); + assert(ch); + assert(nvgpu_atomic_read(&ch->bound) == 0); + + nvgpu_writel(g, ccsr_channel_inst_r(ch->chid), 0); + nvgpu_writel(g, ccsr_channel_r(ch->chid), 0); + + g->ops.channel.bind(ch); + assert(nvgpu_atomic_read(&ch->bound) == 1); + + gv11b_channel_unbind(ch); + + assert(nvgpu_readl(g, (ccsr_channel_inst_r(ch->chid)) & + ccsr_channel_inst_bind_false_f()) != 0); + assert(nvgpu_readl(g, (ccsr_channel_r(ch->chid)) & + ccsr_channel_enable_clr_true_f()) != 0); + assert(nvgpu_atomic_read(&ch->bound) == 0); + + ret = UNIT_SUCCESS; +done: + if (ch) { + nvgpu_channel_close(ch); + } + + return ret; +} + +int test_gv11b_channel_count(struct unit_module *m, + struct gk20a *g, void *args) +{ + int ret = UNIT_FAIL; + + assert(gv11b_channel_count(g) == ccsr_channel__size_1_v()); + ret = UNIT_SUCCESS; +done: + return ret; +} + + +/* note: other branches covered in gk20a_channel_read_state */ +#define F_CHANNEL_READ_ENG_FAULTED BIT(0) +#define F_CHANNEL_READ_STATE_LAST BIT(1) + +static const char *f_channel_read_state[] = { + "eng_faulted" +}; + +int test_gv11b_channel_read_state(struct unit_module *m, + struct gk20a *g, void *args) +{ + bool privileged = false; + u32 runlist_id = NVGPU_INVALID_RUNLIST_ID; + struct nvgpu_channel *ch; + int ret = UNIT_FAIL; + struct nvgpu_channel_hw_state state; + u32 branches; + + ch = nvgpu_channel_open_new(g, runlist_id, + privileged, getpid(), getpid()); + assert(ch); + + for (branches = 0U; branches < F_CHANNEL_READ_STATE_LAST; branches++) { + + bool eng_faulted = false; + u32 v = 0; + + unit_verbose(m, "%s branches=%s\n", + __func__, branches_str(branches, f_channel_read_state)); + + if (branches & F_CHANNEL_READ_ENG_FAULTED) { + eng_faulted = true; + v = ccsr_channel_eng_faulted_true_v() << 23U; + } + + nvgpu_writel(g, ccsr_channel_r(ch->chid), v); + + gv11b_channel_read_state(g, ch, &state); + assert(state.eng_faulted == eng_faulted); + } + + ret = UNIT_SUCCESS; +done: + if (ch) { + nvgpu_channel_close(ch); + } + + return ret; +} + +#define F_CHANNEL_RESET_FAULTED_PBDMA BIT(0) +#define F_CHANNEL_RESET_FAULTED_ENG BIT(1) +#define F_CHANNEL_RESET_FAULTED_LAST BIT(2) + +static const char *f_channel_reset_faulted[] = { + "eng", + "pbdma", +}; + +int test_gv11b_channel_reset_faulted(struct unit_module *m, + struct gk20a *g, void *args) +{ + bool privileged = false; + u32 runlist_id = NVGPU_INVALID_RUNLIST_ID; + struct nvgpu_channel *ch; + int ret = UNIT_FAIL; + u32 branches; + + ch = nvgpu_channel_open_new(g, runlist_id, + privileged, getpid(), getpid()); + assert(ch); + + for (branches = 0U; branches < F_CHANNEL_RESET_FAULTED_LAST; branches++) { + + bool eng; + bool pbdma; + u32 v; + + unit_verbose(m, "%s branches=%s\n", + __func__, branches_str(branches, f_channel_reset_faulted)); + + eng = (branches & F_CHANNEL_RESET_FAULTED_ENG) != 0; + pbdma = (branches & F_CHANNEL_RESET_FAULTED_PBDMA) != 0; + + nvgpu_writel(g, ccsr_channel_r(ch->chid), 0); + + gv11b_channel_reset_faulted(g, ch, eng, pbdma); + + v = nvgpu_readl(g, ccsr_channel_r(ch->chid)); + assert(!eng || ((v & ccsr_channel_eng_faulted_reset_f()) != 0)); + assert(!pbdma || ((v & ccsr_channel_pbdma_faulted_reset_f()) != 0)); + } + + ret = UNIT_SUCCESS; +done: + if (ch) { + nvgpu_channel_close(ch); + } + + return ret; +} + +#define F_CHANNEL_DUMP_DETERMINISTIC BIT(0) +#define F_CHANNEL_DUMP_ENABLED BIT(1) +#define F_CHANNEL_DUMP_BUSY BIT(2) +#define F_CHANNEL_DUMP_SEMA BIT(3) +#define F_CHANNEL_DUMP_LAST BIT(4) + +static const char *f_channel_dump[] = { + "deterministic", + "enabled", + "busy", + "sema", +}; + +static void test_debug_out(void *ctx, const char *str, size_t len) +{ + struct unit_ctx *unit_ctx = ctx; + + unit_ctx->count++; + if (len >= unit_ctx->size || strlen(str) > len) { + unit_ctx->err++; + unit_err(unit_ctx->m, "** oversize string" ); + } else { + unit_verbose(unit_ctx->m, "%s", str); + } +} + +int test_gv11b_channel_debug_dump(struct unit_module *m, + struct gk20a *g, void *args) +{ + bool privileged = false; + u32 runlist_id = NVGPU_INVALID_RUNLIST_ID; + struct nvgpu_channel *ch; + int ret = UNIT_FAIL; + u32 branches; + struct unit_ctx unit_ctx; + struct nvgpu_debug_context o; + + o.fn = test_debug_out; + o.ctx = &unit_ctx; + + unit_ctx.m = m; + unit_ctx.size = sizeof(o.buf); + + ch = nvgpu_channel_open_new(g, runlist_id, + privileged, getpid(), getpid()); + assert(ch); + + for (branches = 0U; branches < F_CHANNEL_DUMP_LAST; branches++) { + + struct nvgpu_channel_dump_info _info, *info = &_info; + + unit_verbose(m, "%s branches=%s\n", + __func__, branches_str(branches, f_channel_dump)); + + memset(info, 0, sizeof(*info)); + + info->chid = ch->chid; + info->tsgid = ch->tsgid; + info->pid = ch->pid; + info->refs = nvgpu_atomic_read(&ch->ref_count); + info->deterministic = (branches & F_CHANNEL_DUMP_DETERMINISTIC) != 0; + info->hw_state.enabled = (branches & F_CHANNEL_DUMP_ENABLED) != 0; + info->hw_state.busy = (branches & F_CHANNEL_DUMP_BUSY) != 0; + info->hw_state.status_string = "fake"; + info->sema.addr = branches & F_CHANNEL_DUMP_SEMA ? 0x1000beef : 0; + + unit_ctx.count = 0; + gv11b_channel_debug_dump(g, &o, info); + +#ifdef CONFIG_DEBUG_FS + assert(unit_ctx.count > 4); + assert(unit_ctx.err == 0); +#endif + } + + + ret = UNIT_SUCCESS; +done: + if (ch) { + nvgpu_channel_close(ch); + } + + return ret; +} + + +struct unit_module_test nvgpu_channel_gv11b_tests[] = { + UNIT_TEST(init_support, test_fifo_init_support, NULL, 0), + UNIT_TEST(unbind, test_gv11b_channel_unbind, NULL, 0), + UNIT_TEST(count, test_gv11b_channel_count, NULL, 0), + UNIT_TEST(read_state, test_gv11b_channel_read_state, NULL, 0), + UNIT_TEST(reset_faulted, test_gv11b_channel_reset_faulted, NULL, 0), + UNIT_TEST(debug_dump, test_gv11b_channel_debug_dump, NULL, 0), + UNIT_TEST(remove_support, test_fifo_remove_support, NULL, 0), +}; + +UNIT_MODULE(nvgpu_channel_gv11b, nvgpu_channel_gv11b_tests, UNIT_PRIO_NVGPU_TEST); diff --git a/userspace/units/fifo/channel/gv11b/nvgpu-channel-gv11b.h b/userspace/units/fifo/channel/gv11b/nvgpu-channel-gv11b.h new file mode 100644 index 000000000..48cf5497c --- /dev/null +++ b/userspace/units/fifo/channel/gv11b/nvgpu-channel-gv11b.h @@ -0,0 +1,146 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef UNIT_NVGPU_CHANNEL_GV11B_H +#define UNIT_NVGPU_CHANNEL_GV11B_H + +#include + +struct unit_module; +struct gk20a; + +/** @addtogroup SWUTS-fifo-channel-gv11b + * @{ + * + * Software Unit Test Specification for fifo/channel/gv11b + */ + +/** + * Test specification for: test_gv11b_channel_unbind + * + * Description: Branch coverage for gv11b_channel_unbind + * + * Test Type: Feature based + * + * Input: test_fifo_init_support() run for this GPU + * + * Steps: + * - Allocate channel. + * - Bind channel with g->ops.channel.bind(). + * - Check that channel is bound (ch->bound == 1). + * - Clear ccsr_channel_inst_r and ccsr_channel_r registers. + * - Unbind channel with gv11b_channel_unbind(). + * - Check that channel is not bound (ch->bound == 0). + * - Check that ccsr registers were programmed to unbind channel. + * + * Output: Returns PASS if all branches gave expected results. FAIL otherwise. + */ +int test_gv11b_channel_unbind(struct unit_module *m, + struct gk20a *g, void *args); + +/** + * Test specification for: test_gv11b_channel_count + * + * Description: Branch coverage for gv11b_channel_count + * + * Test Type: Feature based + * + * Input: test_fifo_init_support() run for this GPU + * + * Steps: + * - Check that number of channel matches H/W manuals definition. + * + * Output: Returns PASS if all branches gave expected results. FAIL otherwise. + */ +int test_gv11b_channel_count(struct unit_module *m, + struct gk20a *g, void *args); + +/** + * Test specification for: test_gv11b_channel_read_state + * + * Description: Branch coverage for gv11b_channel_read_state + * + * Test Type: Feature based + * + * Input: test_fifo_init_support() run for this GPU + * + * Steps: + * - Allocate channel. + * - Set ccsr_channel_r. + * - Read state with gv11b_channel_read_state. + * - Check case w/ and w/o eng_faulted. + * + * Note: other values are checked in gk20a_channel_read_state. + * + * Output: Returns PASS if all branches gave expected results. FAIL otherwise. + */ +int test_gv11b_channel_read_state(struct unit_module *m, + struct gk20a *g, void *args); + +/** + * Test specification for: test_gv11b_channel_reset_faulted + * + * Description: Branch coverage for gv11b_channel_reset_faulted + * + * Test Type: Feature based + * + * Input: test_fifo_init_support() run for this GPU + * + * Steps: + * - Allocate channel. + * - Clear ccsr_channel_r register. + * - Call gv11b_channel_reset_faulted. + * - Check that eng_faulted_reset bit is set when eng is true. + * - Check that pbdma_faulted_reset bit is set when pbdma is true. + * + * Output: Returns PASS if all branches gave expected results. FAIL otherwise. + */ +int test_gv11b_channel_reset_faulted(struct unit_module *m, + struct gk20a *g, void *args); + +/** + * Test specification for: test_gv11b_channel_debug_dump + * + * Description: Branch coverage for gv11b_channel_debug_dump + * + * Test Type: Feature based + * + * Input: test_fifo_init_support() run for this GPU + * + * Steps: + * - Allocate channel. + * - Build nvgpu_channel_dump_info structure. + * - Call gv11b_channel_debug_output, with all combinations of + * channel deterministic, enabled, busy and sema. + * - If gk20a_debug_output actually calls output function, + * check that length of output string does not exceed buffer + * capacity. + * + * Output: Returns PASS if all branches gave expected results. FAIL otherwise. + */ +int test_gv11b_channel_debug_dump(struct unit_module *m, + struct gk20a *g, void *args); + +/** + * @} + */ + +#endif /* UNIT_NVGPU_CHANNEL_GV11B_H */