From 296ff58eb19769260c0e1ae5591fad9a2a8e341f Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 25 Apr 2019 14:29:07 -0700 Subject: [PATCH] gpu: nvgpu: move engine related struct Move from fifo_gk20a.h to engines.h fifo_pbdma_exception_info_gk20a fifo_engine_exception_info_gk20a fifo_engine_info_gk20a Rename fifo_pbdma_exception_info_gk20a -> nvgpu_pbdma_exception_info fifo_engine_exception_info_gk20a -> nvgpu_engine_exception_info fifo_engine_info_gk20a -> nvgpu_engine_info NVGPU_ENGINE_GR_GK20A -> NVGPU_ENGINE_GR NVGPU_ENGINE_GRCE_GK20A -> NVGPU_ENGINE_GRCE NVGPU_ENGINE_ASYNC_CE_GK20A -> NVGPU_ENGINE_ASYNC_CE NVGPU_ENGINE_INVAL_GK20A -> NVGPU_ENGINE_INVAL JIRA NVGPU-2012 Change-Id: I665487721608ff9eacbdebff17d9dbef653de55e Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/2109009 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/fifo/engines.c | 76 +++++++++---------- drivers/gpu/nvgpu/common/fifo/runlist.c | 2 +- .../gpu/nvgpu/common/power_features/cg/cg.c | 4 +- .../gpu/nvgpu/common/vgpu/fifo/fifo_vgpu.c | 2 +- drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | 34 +-------- drivers/gpu/nvgpu/hal/fifo/engines_gm20b.c | 8 +- drivers/gpu/nvgpu/hal/fifo/engines_gp10b.c | 8 +- drivers/gpu/nvgpu/hal/fifo/mmu_fault_gm20b.c | 2 +- .../gpu/nvgpu/hal/fifo/runlist_fifo_gk20a.c | 2 +- drivers/gpu/nvgpu/hal/mc/mc_gm20b.c | 14 ++-- drivers/gpu/nvgpu/hal/mc/mc_gp10b.c | 6 +- drivers/gpu/nvgpu/include/nvgpu/channel.h | 2 +- drivers/gpu/nvgpu/include/nvgpu/engines.h | 45 +++++++++-- drivers/gpu/nvgpu/os/linux/debug_fifo.c | 2 +- drivers/gpu/nvgpu/os/linux/ioctl_channel.c | 4 +- drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c | 10 +-- 16 files changed, 109 insertions(+), 112 deletions(-) diff --git a/drivers/gpu/nvgpu/common/fifo/engines.c b/drivers/gpu/nvgpu/common/fifo/engines.c index 11ee9cd04..20c4b255e 100644 --- a/drivers/gpu/nvgpu/common/fifo/engines.c +++ b/drivers/gpu/nvgpu/common/fifo/engines.c @@ -44,34 +44,34 @@ enum nvgpu_fifo_engine nvgpu_engine_enum_from_type(struct gk20a *g, u32 engine_type) { - enum nvgpu_fifo_engine ret = NVGPU_ENGINE_INVAL_GK20A; + enum nvgpu_fifo_engine ret = NVGPU_ENGINE_INVAL; if ((g->ops.top.is_engine_gr != NULL) && (g->ops.top.is_engine_ce != NULL)) { if (g->ops.top.is_engine_gr(g, engine_type)) { - ret = NVGPU_ENGINE_GR_GK20A; + ret = NVGPU_ENGINE_GR; } else if (g->ops.top.is_engine_ce(g, engine_type)) { /* Lets consider all the CE engine have separate * runlist at this point. We can identify the - * NVGPU_ENGINE_GRCE_GK20A type CE using runlist_id + * NVGPU_ENGINE_GRCE type CE using runlist_id * comparsion logic with GR runlist_id in * init_info() */ - ret = NVGPU_ENGINE_ASYNC_CE_GK20A; + ret = NVGPU_ENGINE_ASYNC_CE; } else { - ret = NVGPU_ENGINE_INVAL_GK20A; + ret = NVGPU_ENGINE_INVAL; } } return ret; } -struct fifo_engine_info_gk20a *nvgpu_engine_get_active_eng_info( +struct nvgpu_engine_info *nvgpu_engine_get_active_eng_info( struct gk20a *g, u32 engine_id) { struct fifo_gk20a *f = NULL; u32 engine_id_idx; - struct fifo_engine_info_gk20a *info = NULL; + struct nvgpu_engine_info *info = NULL; if (g == NULL) { return info; @@ -106,10 +106,10 @@ u32 nvgpu_engine_get_ids(struct gk20a *g, u32 instance_cnt = 0; u32 engine_id_idx; u32 active_engine_id = 0; - struct fifo_engine_info_gk20a *info = NULL; + struct nvgpu_engine_info *info = NULL; if ((g == NULL) || (engine_id_sz == 0U) || - (engine_enum == NVGPU_ENGINE_INVAL_GK20A)) { + (engine_enum == NVGPU_ENGINE_INVAL)) { return instance_cnt; } @@ -169,7 +169,7 @@ u32 nvgpu_engine_get_gr_id(struct gk20a *g) /* Consider 1st available GR engine */ gr_engine_cnt = nvgpu_engine_get_ids(g, &gr_engine_id, - 1, NVGPU_ENGINE_GR_GK20A); + 1, NVGPU_ENGINE_GR); if (gr_engine_cnt == 0U) { nvgpu_err(g, "No GR engine available on this device!"); @@ -180,7 +180,7 @@ u32 nvgpu_engine_get_gr_id(struct gk20a *g) u32 nvgpu_engine_act_interrupt_mask(struct gk20a *g, u32 act_eng_id) { - struct fifo_engine_info_gk20a *engine_info = NULL; + struct nvgpu_engine_info *engine_info = NULL; engine_info = nvgpu_engine_get_active_eng_info(g, act_eng_id); if (engine_info != NULL) { @@ -202,8 +202,8 @@ u32 nvgpu_engine_interrupt_mask(struct gk20a *g) active_engine_id = g->fifo.active_engines_list[i]; intr_mask = g->fifo.engine_info[active_engine_id].intr_mask; engine_enum = g->fifo.engine_info[active_engine_id].engine_enum; - if (((engine_enum == NVGPU_ENGINE_GRCE_GK20A) || - (engine_enum == NVGPU_ENGINE_ASYNC_CE_GK20A)) && + if (((engine_enum == NVGPU_ENGINE_GRCE) || + (engine_enum == NVGPU_ENGINE_ASYNC_CE)) && ((g->ops.ce.isr_stall == NULL) || (g->ops.ce.isr_nonstall == NULL))) { continue; @@ -221,7 +221,7 @@ u32 nvgpu_engine_get_all_ce_reset_mask(struct gk20a *g) enum nvgpu_fifo_engine engine_enum; struct fifo_gk20a *f = NULL; u32 engine_id_idx; - struct fifo_engine_info_gk20a *engine_info; + struct nvgpu_engine_info *engine_info; u32 active_engine_id = 0; if (g == NULL) { @@ -236,8 +236,8 @@ u32 nvgpu_engine_get_all_ce_reset_mask(struct gk20a *g) engine_info = &f->engine_info[active_engine_id]; engine_enum = engine_info->engine_enum; - if ((engine_enum == NVGPU_ENGINE_GRCE_GK20A) || - (engine_enum == NVGPU_ENGINE_ASYNC_CE_GK20A)) { + if ((engine_enum == NVGPU_ENGINE_GRCE) || + (engine_enum == NVGPU_ENGINE_ASYNC_CE)) { reset_mask |= engine_info->reset_mask; } } @@ -248,7 +248,7 @@ u32 nvgpu_engine_get_all_ce_reset_mask(struct gk20a *g) #ifdef NVGPU_ENGINE int nvgpu_engine_enable_activity(struct gk20a *g, - struct fifo_engine_info_gk20a *eng_info) + struct nvgpu_engine_info *eng_info) { nvgpu_log(g, gpu_dbg_info, "start"); @@ -277,7 +277,7 @@ int nvgpu_engine_enable_activity_all(struct gk20a *g) } int nvgpu_engine_disable_activity(struct gk20a *g, - struct fifo_engine_info_gk20a *eng_info, + struct nvgpu_engine_info *eng_info, bool wait_for_idle) { u32 pbdma_chid = FIFO_INVAL_CHANNEL_ID; @@ -506,8 +506,8 @@ void nvgpu_engine_cleanup_sw(struct gk20a *g) void nvgpu_engine_reset(struct gk20a *g, u32 engine_id) { - enum nvgpu_fifo_engine engine_enum = NVGPU_ENGINE_INVAL_GK20A; - struct fifo_engine_info_gk20a *engine_info; + enum nvgpu_fifo_engine engine_enum = NVGPU_ENGINE_INVAL; + struct nvgpu_engine_info *engine_info; nvgpu_log_fn(g, " "); @@ -521,11 +521,11 @@ void nvgpu_engine_reset(struct gk20a *g, u32 engine_id) engine_enum = engine_info->engine_enum; } - if (engine_enum == NVGPU_ENGINE_INVAL_GK20A) { + if (engine_enum == NVGPU_ENGINE_INVAL) { nvgpu_err(g, "unsupported engine_id %d", engine_id); } - if (engine_enum == NVGPU_ENGINE_GR_GK20A) { + if (engine_enum == NVGPU_ENGINE_GR) { if (nvgpu_pg_elpg_disable(g) != 0 ) { nvgpu_err(g, "failed to set disable elpg"); } @@ -566,8 +566,8 @@ void nvgpu_engine_reset(struct gk20a *g, u32 engine_id) } } - if ((engine_enum == NVGPU_ENGINE_GRCE_GK20A) || - (engine_enum == NVGPU_ENGINE_ASYNC_CE_GK20A)) { + if ((engine_enum == NVGPU_ENGINE_GRCE) || + (engine_enum == NVGPU_ENGINE_ASYNC_CE)) { g->ops.mc.reset(g, engine_info->reset_mask); } } @@ -578,7 +578,7 @@ u32 nvgpu_engine_get_fast_ce_runlist_id(struct gk20a *g) enum nvgpu_fifo_engine engine_enum; struct fifo_gk20a *f = NULL; u32 engine_id_idx; - struct fifo_engine_info_gk20a *engine_info; + struct nvgpu_engine_info *engine_info; u32 active_engine_id = 0U; if (g == NULL) { @@ -594,7 +594,7 @@ u32 nvgpu_engine_get_fast_ce_runlist_id(struct gk20a *g) engine_enum = engine_info->engine_enum; /* select last available ASYNC_CE if available */ - if (engine_enum == NVGPU_ENGINE_ASYNC_CE_GK20A) { + if (engine_enum == NVGPU_ENGINE_ASYNC_CE) { ce_runlist_id = engine_info->runlist_id; } } @@ -606,12 +606,12 @@ u32 nvgpu_engine_get_gr_runlist_id(struct gk20a *g) { u32 gr_engine_cnt = 0; u32 gr_engine_id = FIFO_INVAL_ENGINE_ID; - struct fifo_engine_info_gk20a *engine_info; + struct nvgpu_engine_info *engine_info; u32 gr_runlist_id = U32_MAX; /* Consider 1st available GR engine */ gr_engine_cnt = nvgpu_engine_get_ids(g, &gr_engine_id, - 1, NVGPU_ENGINE_GR_GK20A); + 1, NVGPU_ENGINE_GR); if (gr_engine_cnt == 0U) { nvgpu_err(g, @@ -638,7 +638,7 @@ bool nvgpu_engine_is_valid_runlist_id(struct gk20a *g, u32 runlist_id) struct fifo_gk20a *f = NULL; u32 engine_id_idx; u32 active_engine_id; - struct fifo_engine_info_gk20a *engine_info; + struct nvgpu_engine_info *engine_info; if (g == NULL) { return false; @@ -666,7 +666,7 @@ bool nvgpu_engine_is_valid_runlist_id(struct gk20a *g, u32 runlist_id) u32 nvgpu_engine_id_to_mmu_fault_id(struct gk20a *g, u32 engine_id) { u32 fault_id = FIFO_INVAL_ENGINE_ID; - struct fifo_engine_info_gk20a *engine_info; + struct nvgpu_engine_info *engine_info; engine_info = nvgpu_engine_get_active_eng_info(g, engine_id); @@ -683,7 +683,7 @@ u32 nvgpu_engine_mmu_fault_id_to_engine_id(struct gk20a *g, u32 fault_id) { u32 engine_id; u32 active_engine_id; - struct fifo_engine_info_gk20a *engine_info; + struct nvgpu_engine_info *engine_info; struct fifo_gk20a *f = &g->fifo; for (engine_id = 0; engine_id < f->num_engines; engine_id++) { @@ -748,7 +748,7 @@ int nvgpu_engine_init_info(struct fifo_gk20a *f) f->num_engines = 0; if (g->ops.top.get_device_info != NULL) { struct nvgpu_device_info dev_info; - struct fifo_engine_info_gk20a *info; + struct nvgpu_engine_info *info; ret = g->ops.top.get_device_info(g, &dev_info, NVGPU_ENGINE_GRAPHICS, 0); @@ -905,8 +905,8 @@ u32 nvgpu_engine_get_runlist_busy_engines(struct gk20a *g, u32 runlist_id) bool nvgpu_engine_should_defer_reset(struct gk20a *g, u32 engine_id, u32 engine_subid, bool fake_fault) { - enum nvgpu_fifo_engine engine_enum = NVGPU_ENGINE_INVAL_GK20A; - struct fifo_engine_info_gk20a *engine_info; + enum nvgpu_fifo_engine engine_enum = NVGPU_ENGINE_INVAL; + struct nvgpu_engine_info *engine_info; if (g == NULL) { return false; @@ -918,7 +918,7 @@ bool nvgpu_engine_should_defer_reset(struct gk20a *g, u32 engine_id, engine_enum = engine_info->engine_enum; } - if (engine_enum == NVGPU_ENGINE_INVAL_GK20A) { + if (engine_enum == NVGPU_ENGINE_INVAL) { return false; } @@ -936,7 +936,7 @@ bool nvgpu_engine_should_defer_reset(struct gk20a *g, u32 engine_id, return false; } - if (engine_enum != NVGPU_ENGINE_GR_GK20A) { + if (engine_enum != NVGPU_ENGINE_GR) { return false; } @@ -965,7 +965,7 @@ u32 nvgpu_engine_mmu_fault_id_to_eng_id_and_veid(struct gk20a *g, { u32 engine_id; u32 act_eng_id; - struct fifo_engine_info_gk20a *engine_info; + struct nvgpu_engine_info *engine_info; struct fifo_gk20a *f = &g->fifo; @@ -973,7 +973,7 @@ u32 nvgpu_engine_mmu_fault_id_to_eng_id_and_veid(struct gk20a *g, act_eng_id = f->active_engines_list[engine_id]; engine_info = &g->fifo.engine_info[act_eng_id]; - if (act_eng_id == NVGPU_ENGINE_GR_GK20A) { + if (act_eng_id == NVGPU_ENGINE_GR) { /* get faulted subctx id */ *veid = nvgpu_engine_mmu_fault_id_to_veid(g, mmu_fault_id, engine_info->fault_id); diff --git a/drivers/gpu/nvgpu/common/fifo/runlist.c b/drivers/gpu/nvgpu/common/fifo/runlist.c index 5f39c3134..57316f186 100644 --- a/drivers/gpu/nvgpu/common/fifo/runlist.c +++ b/drivers/gpu/nvgpu/common/fifo/runlist.c @@ -658,7 +658,7 @@ void nvgpu_runlist_cleanup_sw(struct gk20a *g) static void nvgpu_init_runlist_enginfo(struct gk20a *g, struct fifo_gk20a *f) { struct nvgpu_runlist_info *runlist; - struct fifo_engine_info_gk20a *engine_info; + struct nvgpu_engine_info *engine_info; u32 i, active_engine_id, pbdma_id, engine_id; nvgpu_log_fn(g, " "); diff --git a/drivers/gpu/nvgpu/common/power_features/cg/cg.c b/drivers/gpu/nvgpu/common/power_features/cg/cg.c index e546ecb1d..85d487bd7 100644 --- a/drivers/gpu/nvgpu/common/power_features/cg/cg.c +++ b/drivers/gpu/nvgpu/common/power_features/cg/cg.c @@ -32,7 +32,7 @@ static void nvgpu_cg_set_mode(struct gk20a *g, int cgmode, int mode_config) { u32 engine_idx; u32 active_engine_id = 0; - struct fifo_engine_info_gk20a *engine_info = NULL; + struct nvgpu_engine_info *engine_info = NULL; struct fifo_gk20a *f = &g->fifo; nvgpu_log_fn(g, " "); @@ -43,7 +43,7 @@ static void nvgpu_cg_set_mode(struct gk20a *g, int cgmode, int mode_config) /* gr_engine supports both BLCG and ELCG */ if ((cgmode == BLCG_MODE) && (engine_info->engine_enum == - NVGPU_ENGINE_GR_GK20A)) { + NVGPU_ENGINE_GR)) { g->ops.therm.init_blcg_mode(g, (u32)mode_config, active_engine_id); break; diff --git a/drivers/gpu/nvgpu/common/vgpu/fifo/fifo_vgpu.c b/drivers/gpu/nvgpu/common/vgpu/fifo/fifo_vgpu.c index 43374d264..57df2e462 100644 --- a/drivers/gpu/nvgpu/common/vgpu/fifo/fifo_vgpu.c +++ b/drivers/gpu/nvgpu/common/vgpu/fifo/fifo_vgpu.c @@ -176,7 +176,7 @@ int vgpu_fifo_init_engine_info(struct fifo_gk20a *f) f->num_engines = engines->num_engines; for (i = 0; i < f->num_engines; i++) { - struct fifo_engine_info_gk20a *info = + struct nvgpu_engine_info *info = &f->engine_info[engines->info[i].engine_id]; if (engines->info[i].engine_id >= f->max_engines) { diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h index 49c10661e..8cc88f5e2 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h @@ -51,38 +51,6 @@ struct tsg_gk20a; #define FIFO_PROFILING_ENTRIES 16384U #endif -/* generally corresponds to the "pbdma" engine */ - -struct fifo_pbdma_exception_info_gk20a { - u32 status_r; /* raw register value from hardware */ - u32 id, next_id; - u32 chan_status_v; /* raw value from hardware */ - bool id_is_chid, next_id_is_chid; - bool chsw_in_progress; -}; - -struct fifo_engine_exception_info_gk20a { - u32 status_r; /* raw register value from hardware */ - u32 id, next_id; - u32 ctx_status_v; /* raw value from hardware */ - bool id_is_chid, next_id_is_chid; - bool faulted, idle, ctxsw_in_progress; -}; - -struct fifo_engine_info_gk20a { - u32 engine_id; - u32 runlist_id; - u32 intr_mask; - u32 reset_mask; - u32 pbdma_id; - u32 inst_id; - u32 pri_base; - u32 fault_id; - enum nvgpu_fifo_engine engine_enum; - struct fifo_pbdma_exception_info_gk20a pbdma_exception_info; - struct fifo_engine_exception_info_gk20a engine_exception_info; -}; - enum { PROFILE_IOCTL_ENTRY = 0U, PROFILE_ENTRY, @@ -106,7 +74,7 @@ struct fifo_gk20a { unsigned int num_pbdma; u32 *pbdma_map; - struct fifo_engine_info_gk20a *engine_info; + struct nvgpu_engine_info *engine_info; u32 max_engines; u32 num_engines; u32 *active_engines_list; diff --git a/drivers/gpu/nvgpu/hal/fifo/engines_gm20b.c b/drivers/gpu/nvgpu/hal/fifo/engines_gm20b.c index d54d6b78f..9b7a698c7 100644 --- a/drivers/gpu/nvgpu/hal/fifo/engines_gm20b.c +++ b/drivers/gpu/nvgpu/hal/fifo/engines_gm20b.c @@ -51,7 +51,7 @@ int gm20b_engine_init_ce_info(struct fifo_gk20a *f) if (g->ops.top.get_device_info != NULL) { for (i = NVGPU_ENGINE_COPY0; i <= NVGPU_ENGINE_COPY2; i++) { struct nvgpu_device_info dev_info; - struct fifo_engine_info_gk20a *info; + struct nvgpu_engine_info *info; ret = g->ops.top.get_device_info(g, &dev_info, i, 0); if (ret != 0) { @@ -81,10 +81,10 @@ int gm20b_engine_init_ce_info(struct fifo_gk20a *f) dev_info.engine_type); /* GR and GR_COPY shares same runlist_id */ - if ((engine_enum == NVGPU_ENGINE_ASYNC_CE_GK20A) && + if ((engine_enum == NVGPU_ENGINE_ASYNC_CE) && (gr_runlist_id == dev_info.runlist_id)) { - engine_enum = NVGPU_ENGINE_GRCE_GK20A; + engine_enum = NVGPU_ENGINE_GRCE; } info->engine_enum = engine_enum; @@ -95,7 +95,7 @@ int gm20b_engine_init_ce_info(struct fifo_gk20a *f) if ((dev_info.fault_id == 0U) && (engine_enum == - NVGPU_ENGINE_GRCE_GK20A)) { + NVGPU_ENGINE_GRCE)) { dev_info.fault_id = 0x1b; } info->fault_id = dev_info.fault_id; diff --git a/drivers/gpu/nvgpu/hal/fifo/engines_gp10b.c b/drivers/gpu/nvgpu/hal/fifo/engines_gp10b.c index c9150bcca..d6a61d5fd 100644 --- a/drivers/gpu/nvgpu/hal/fifo/engines_gp10b.c +++ b/drivers/gpu/nvgpu/hal/fifo/engines_gp10b.c @@ -52,7 +52,7 @@ int gp10b_engine_init_ce_info(struct fifo_gk20a *f) for (i = 0; i < lce_num_entries; i++) { struct nvgpu_device_info dev_info; - struct fifo_engine_info_gk20a *info; + struct nvgpu_engine_info *info; ret = g->ops.top.get_device_info(g, &dev_info, NVGPU_ENGINE_LCE, i); @@ -78,10 +78,10 @@ int gp10b_engine_init_ce_info(struct fifo_gk20a *f) g, dev_info.engine_type); /* GR and GR_COPY shares same runlist_id */ - if ((engine_enum == NVGPU_ENGINE_ASYNC_CE_GK20A) && + if ((engine_enum == NVGPU_ENGINE_ASYNC_CE) && (gr_runlist_id == dev_info.runlist_id)) { - engine_enum = NVGPU_ENGINE_GRCE_GK20A; + engine_enum = NVGPU_ENGINE_GRCE; } info->engine_enum = engine_enum; @@ -91,7 +91,7 @@ int gp10b_engine_init_ce_info(struct fifo_gk20a *f) } if ((dev_info.fault_id == 0U) && - (engine_enum == NVGPU_ENGINE_GRCE_GK20A)) { + (engine_enum == NVGPU_ENGINE_GRCE)) { dev_info.fault_id = 0x1b; } info->fault_id = dev_info.fault_id; diff --git a/drivers/gpu/nvgpu/hal/fifo/mmu_fault_gm20b.c b/drivers/gpu/nvgpu/hal/fifo/mmu_fault_gm20b.c index 162311f3f..9823a7f01 100644 --- a/drivers/gpu/nvgpu/hal/fifo/mmu_fault_gm20b.c +++ b/drivers/gpu/nvgpu/hal/fifo/mmu_fault_gm20b.c @@ -67,7 +67,7 @@ static inline u32 gm20b_engine_id_to_fault_id(struct gk20a *g, u32 engine_id) { u32 fault_id = INVAL_ID; - struct fifo_engine_info_gk20a *engine_info; + struct nvgpu_engine_info *engine_info; engine_info = nvgpu_engine_get_active_eng_info(g, engine_id); diff --git a/drivers/gpu/nvgpu/hal/fifo/runlist_fifo_gk20a.c b/drivers/gpu/nvgpu/hal/fifo/runlist_fifo_gk20a.c index 1d300916b..abe5888e2 100644 --- a/drivers/gpu/nvgpu/hal/fifo/runlist_fifo_gk20a.c +++ b/drivers/gpu/nvgpu/hal/fifo/runlist_fifo_gk20a.c @@ -150,7 +150,7 @@ int gk20a_fifo_reschedule_preempt_next(struct channel_gk20a *ch, struct nvgpu_engine_status_info engine_status; if (1U != nvgpu_engine_get_ids( - g, &gr_eng_id, 1, NVGPU_ENGINE_GR_GK20A)) { + g, &gr_eng_id, 1, NVGPU_ENGINE_GR)) { return ret; } if ((runlist->eng_bitmask & BIT32(gr_eng_id)) == 0U) { diff --git a/drivers/gpu/nvgpu/hal/mc/mc_gm20b.c b/drivers/gpu/nvgpu/hal/mc/mc_gm20b.c index 14d7fefd3..5c938a934 100644 --- a/drivers/gpu/nvgpu/hal/mc/mc_gm20b.c +++ b/drivers/gpu/nvgpu/hal/mc/mc_gm20b.c @@ -57,14 +57,14 @@ void gm20b_mc_isr_stall(struct gk20a *g) } engine_enum = g->fifo.engine_info[act_eng_id].engine_enum; /* GR Engine */ - if (engine_enum == NVGPU_ENGINE_GR_GK20A) { + if (engine_enum == NVGPU_ENGINE_GR) { nvgpu_pg_elpg_protected_call(g, g->ops.gr.intr.stall_isr(g)); } /* CE Engine */ - if (((engine_enum == NVGPU_ENGINE_GRCE_GK20A) || - (engine_enum == NVGPU_ENGINE_ASYNC_CE_GK20A)) && + if (((engine_enum == NVGPU_ENGINE_GRCE) || + (engine_enum == NVGPU_ENGINE_ASYNC_CE)) && (g->ops.ce.isr_stall != NULL)) { g->ops.ce.isr_stall(g, g->fifo.engine_info[act_eng_id].inst_id, @@ -103,7 +103,7 @@ u32 gm20b_mc_isr_nonstall(struct gk20a *g) } for (eng_id = 0U; eng_id < g->fifo.num_engines; eng_id++) { - struct fifo_engine_info_gk20a *engine_info; + struct nvgpu_engine_info *engine_info; act_eng_id = g->fifo.active_engines_list[eng_id]; engine_info = &g->fifo.engine_info[act_eng_id]; @@ -111,12 +111,12 @@ u32 gm20b_mc_isr_nonstall(struct gk20a *g) if ((mc_intr_1 & engine_info->intr_mask) != 0U) { engine_enum = engine_info->engine_enum; /* GR Engine */ - if (engine_enum == NVGPU_ENGINE_GR_GK20A) { + if (engine_enum == NVGPU_ENGINE_GR) { ops |= g->ops.gr.intr.nonstall_isr(g); } /* CE Engine */ - if (((engine_enum == NVGPU_ENGINE_GRCE_GK20A) || - (engine_enum == NVGPU_ENGINE_ASYNC_CE_GK20A)) && + if (((engine_enum == NVGPU_ENGINE_GRCE) || + (engine_enum == NVGPU_ENGINE_ASYNC_CE)) && (g->ops.ce.isr_nonstall != NULL)) { ops |= g->ops.ce.isr_nonstall(g, engine_info->inst_id, diff --git a/drivers/gpu/nvgpu/hal/mc/mc_gp10b.c b/drivers/gpu/nvgpu/hal/mc/mc_gp10b.c index 854722901..f7b332984 100644 --- a/drivers/gpu/nvgpu/hal/mc/mc_gp10b.c +++ b/drivers/gpu/nvgpu/hal/mc/mc_gp10b.c @@ -110,14 +110,14 @@ void mc_gp10b_isr_stall(struct gk20a *g) } engine_enum = g->fifo.engine_info[act_eng_id].engine_enum; /* GR Engine */ - if (engine_enum == NVGPU_ENGINE_GR_GK20A) { + if (engine_enum == NVGPU_ENGINE_GR) { nvgpu_pg_elpg_protected_call(g, g->ops.gr.intr.stall_isr(g)); } /* CE Engine */ - if (((engine_enum == NVGPU_ENGINE_GRCE_GK20A) || - (engine_enum == NVGPU_ENGINE_ASYNC_CE_GK20A)) && + if (((engine_enum == NVGPU_ENGINE_GRCE) || + (engine_enum == NVGPU_ENGINE_ASYNC_CE)) && (g->ops.ce.isr_stall != NULL)) { g->ops.ce.isr_stall(g, g->fifo.engine_info[act_eng_id].inst_id, diff --git a/drivers/gpu/nvgpu/include/nvgpu/channel.h b/drivers/gpu/nvgpu/include/nvgpu/channel.h index 731d2a33e..1712f6bc7 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/channel.h +++ b/drivers/gpu/nvgpu/include/nvgpu/channel.h @@ -460,7 +460,7 @@ struct channel_gk20a *__must_check _gk20a_channel_from_id(struct gk20a *g, int gk20a_wait_channel_idle(struct channel_gk20a *ch); -/* runlist_id -1 is synonym for NVGPU_ENGINE_GR_GK20A runlist id */ +/* runlist_id -1 is synonym for NVGPU_ENGINE_GR runlist id */ struct channel_gk20a *gk20a_open_new_channel(struct gk20a *g, u32 runlist_id, bool is_privileged_channel, diff --git a/drivers/gpu/nvgpu/include/nvgpu/engines.h b/drivers/gpu/nvgpu/include/nvgpu/engines.h index 2ebf81927..250181a26 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/engines.h +++ b/drivers/gpu/nvgpu/include/nvgpu/engines.h @@ -26,20 +26,49 @@ #include struct gk20a; -struct fifo_engine_info_gk20a; struct fifo_gk20a; enum nvgpu_fifo_engine { - NVGPU_ENGINE_GR_GK20A = 0U, - NVGPU_ENGINE_GRCE_GK20A = 1U, - NVGPU_ENGINE_ASYNC_CE_GK20A = 2U, - NVGPU_ENGINE_INVAL_GK20A = 3U, + NVGPU_ENGINE_GR = 0U, + NVGPU_ENGINE_GRCE = 1U, + NVGPU_ENGINE_ASYNC_CE = 2U, + NVGPU_ENGINE_INVAL = 3U, +}; + +struct nvgpu_pbdma_exception_info { + u32 status_r; /* raw register value from hardware */ + u32 id, next_id; + u32 chan_status_v; /* raw value from hardware */ + bool id_is_chid, next_id_is_chid; + bool chsw_in_progress; +}; + +struct nvgpu_engine_exception_info { + u32 status_r; /* raw register value from hardware */ + u32 id, next_id; + u32 ctx_status_v; /* raw value from hardware */ + bool id_is_chid, next_id_is_chid; + bool faulted, idle, ctxsw_in_progress; +}; + +struct nvgpu_engine_info { + u32 engine_id; + u32 runlist_id; + u32 intr_mask; + u32 reset_mask; + u32 pbdma_id; + u32 inst_id; + u32 pri_base; + u32 fault_id; + enum nvgpu_fifo_engine engine_enum; + struct nvgpu_pbdma_exception_info pbdma_exception_info; + struct nvgpu_engine_exception_info engine_exception_info; }; enum nvgpu_fifo_engine nvgpu_engine_enum_from_type(struct gk20a *g, u32 engine_type); -struct fifo_engine_info_gk20a *nvgpu_engine_get_active_eng_info( +struct nvgpu_engine_info *nvgpu_engine_get_active_eng_info( struct gk20a *g, u32 engine_id); u32 nvgpu_engine_get_ids(struct gk20a *g, @@ -55,10 +84,10 @@ int nvgpu_engine_setup_sw(struct gk20a *g); void nvgpu_engine_cleanup_sw(struct gk20a *g); int nvgpu_engine_enable_activity(struct gk20a *g, - struct fifo_engine_info_gk20a *eng_info); + struct nvgpu_engine_info *eng_info); int nvgpu_engine_enable_activity_all(struct gk20a *g); int nvgpu_engine_disable_activity(struct gk20a *g, - struct fifo_engine_info_gk20a *eng_info, + struct nvgpu_engine_info *eng_info, bool wait_for_idle); int nvgpu_engine_disable_activity_all(struct gk20a *g, bool wait_for_idle); diff --git a/drivers/gpu/nvgpu/os/linux/debug_fifo.c b/drivers/gpu/nvgpu/os/linux/debug_fifo.c index dfe0e4d4b..f53df4798 100644 --- a/drivers/gpu/nvgpu/os/linux/debug_fifo.c +++ b/drivers/gpu/nvgpu/os/linux/debug_fifo.c @@ -64,7 +64,7 @@ static int gk20a_fifo_sched_debugfs_seq_show( struct channel_gk20a *ch = v; struct tsg_gk20a *tsg = NULL; - struct fifo_engine_info_gk20a *engine_info; + struct nvgpu_engine_info *engine_info; struct nvgpu_runlist_info *runlist; u32 runlist_id; int ret = SEQ_SKIP; diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_channel.c b/drivers/gpu/nvgpu/os/linux/ioctl_channel.c index 902105a80..6b7120439 100644 --- a/drivers/gpu/nvgpu/os/linux/ioctl_channel.c +++ b/drivers/gpu/nvgpu/os/linux/ioctl_channel.c @@ -431,7 +431,7 @@ channel_release: return 0; } -/* note: runlist_id -1 is synonym for the NVGPU_ENGINE_GR_GK20A runlist id */ +/* note: runlist_id -1 is synonym for the NVGPU_ENGINE_GR runlist id */ static int __gk20a_channel_open(struct gk20a *g, struct file *filp, s32 runlist_id) { @@ -444,7 +444,7 @@ static int __gk20a_channel_open(struct gk20a *g, nvgpu_assert(runlist_id >= -1); if (runlist_id == -1) { - tmp_runlist_id = NVGPU_ENGINE_GR_GK20A; + tmp_runlist_id = NVGPU_ENGINE_GR; } else { tmp_runlist_id = runlist_id; } diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c b/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c index 0ad257177..47602d541 100644 --- a/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c +++ b/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c @@ -911,7 +911,7 @@ static int nvgpu_gpu_get_engine_info( struct nvgpu_gpu_get_engine_info_args *args) { int err = 0; - u32 engine_enum = NVGPU_ENGINE_INVAL_GK20A; + u32 engine_enum = NVGPU_ENGINE_INVAL; u32 report_index = 0; u32 engine_id_idx; const u32 max_buffer_engines = args->engine_info_buf_size / @@ -922,7 +922,7 @@ static int nvgpu_gpu_get_engine_info( for (engine_id_idx = 0; engine_id_idx < g->fifo.num_engines; ++engine_id_idx) { u32 active_engine_id = g->fifo.active_engines_list[engine_id_idx]; - const struct fifo_engine_info_gk20a *src_info = + const struct nvgpu_engine_info *src_info = &g->fifo.engine_info[active_engine_id]; struct nvgpu_gpu_get_engine_info_item dst_info; @@ -931,15 +931,15 @@ static int nvgpu_gpu_get_engine_info( engine_enum = src_info->engine_enum; switch (engine_enum) { - case NVGPU_ENGINE_GR_GK20A: + case NVGPU_ENGINE_GR: dst_info.engine_id = NVGPU_GPU_ENGINE_ID_GR; break; - case NVGPU_ENGINE_GRCE_GK20A: + case NVGPU_ENGINE_GRCE: dst_info.engine_id = NVGPU_GPU_ENGINE_ID_GR_COPY; break; - case NVGPU_ENGINE_ASYNC_CE_GK20A: + case NVGPU_ENGINE_ASYNC_CE: dst_info.engine_id = NVGPU_GPU_ENGINE_ID_ASYNC_COPY; break;