diff --git a/drivers/gpu/nvgpu/common/fifo/engines.c b/drivers/gpu/nvgpu/common/fifo/engines.c
index 09c9bfeec..cbb5e8817 100644
--- a/drivers/gpu/nvgpu/common/fifo/engines.c
+++ b/drivers/gpu/nvgpu/common/fifo/engines.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2022, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -509,10 +509,6 @@ void nvgpu_engine_reset(struct gk20a *g, u32 engine_id)
 
 	nvgpu_log_fn(g, " ");
 
-	if (g == NULL) {
-		return;
-	}
-
 	nvgpu_swprofile_begin_sample(prof);
 
 	dev = nvgpu_engine_get_active_eng_info(g, engine_id);
diff --git a/drivers/gpu/nvgpu/common/fifo/tsg.c b/drivers/gpu/nvgpu/common/fifo/tsg.c
index ad3405c63..2c16776dc 100644
--- a/drivers/gpu/nvgpu/common/fifo/tsg.c
+++ b/drivers/gpu/nvgpu/common/fifo/tsg.c
@@ -1180,7 +1180,7 @@ int nvgpu_tsg_set_mmu_debug_mode(struct nvgpu_channel *ch, bool enable)
 	u32 fb_refcnt;
 	struct nvgpu_tsg *tsg = nvgpu_tsg_from_ch(ch);
 
-	if ((ch == NULL) || (tsg == NULL)) {
+	if (tsg == NULL) {
 		return -EINVAL;
 	}
 	g = ch->g;
diff --git a/drivers/gpu/nvgpu/common/gr/global_ctx.c b/drivers/gpu/nvgpu/common/gr/global_ctx.c
index f434cede8..62ab255d3 100644
--- a/drivers/gpu/nvgpu/common/gr/global_ctx.c
+++ b/drivers/gpu/nvgpu/common/gr/global_ctx.c
@@ -260,9 +260,7 @@ static int nvgpu_gr_global_ctx_buffer_sys_alloc(struct gk20a *g,
 
 	err = nvgpu_gr_global_ctx_buffer_alloc_sys(g, desc,
 		NVGPU_GR_GLOBAL_CTX_PRIV_ACCESS_MAP);
-	if (err != 0) {
-		goto fail;
-	}
+
 fail:
 	return err;
 }
diff --git a/drivers/gpu/nvgpu/common/init/nvgpu_init.c b/drivers/gpu/nvgpu/common/init/nvgpu_init.c
index b7785356a..745b8a122 100644
--- a/drivers/gpu/nvgpu/common/init/nvgpu_init.c
+++ b/drivers/gpu/nvgpu/common/init/nvgpu_init.c
@@ -347,8 +347,9 @@ int nvgpu_prepare_poweroff(struct gk20a *g)
 	}
 
 #ifdef CONFIG_NVGPU_GSP_STRESS_TEST
-	ret = nvgpu_gsp_stress_test_halt(g, true);
-	if (ret != 0) {
+	tmp_ret = nvgpu_gsp_stress_test_halt(g, true);
+	if (tmp_ret != 0) {
+		ret = tmp_ret;
 		nvgpu_err(g, "Failed to halt GSP stress test");
 	}
 #endif
diff --git a/drivers/gpu/nvgpu/common/mm/nvgpu_mem.c b/drivers/gpu/nvgpu/common/mm/nvgpu_mem.c
index 6fb423356..089736053 100644
--- a/drivers/gpu/nvgpu/common/mm/nvgpu_mem.c
+++ b/drivers/gpu/nvgpu/common/mm/nvgpu_mem.c
@@ -41,19 +41,6 @@ u32 nvgpu_aperture_mask_raw(struct gk20a *g, enum nvgpu_aperture aperture,
 {
 	u32 ret_mask = 0;
 
-	if ((aperture == APERTURE_INVALID) || (aperture >= APERTURE_MAX_ENUM)) {
-		nvgpu_do_assert_print(g, "Bad aperture");
-		return 0;
-	}
-
-	/*
-	 * Some iGPUs treat sysmem (i.e SoC DRAM) as vidmem. In these cases the
-	 * "sysmem" aperture should really be translated to VIDMEM.
-	 */
-	if (!nvgpu_is_enabled(g, NVGPU_MM_HONORS_APERTURE)) {
-		aperture = APERTURE_VIDMEM;
-	}
-
 	switch (aperture) {
 	case APERTURE_SYSMEM_COH:
 		ret_mask = sysmem_coh_mask;
@@ -69,6 +56,15 @@ u32 nvgpu_aperture_mask_raw(struct gk20a *g, enum nvgpu_aperture aperture,
 		ret_mask = 0;
 		break;
 	}
+
+	/*
+	 * Some iGPUs treat sysmem (i.e SoC DRAM) as vidmem. In these cases the
+	 * "sysmem" aperture should really be translated to VIDMEM.
+	 */
+	if (!nvgpu_is_enabled(g, NVGPU_MM_HONORS_APERTURE) && ret_mask != 0) {
+		ret_mask = vidmem_mask;
+	}
+
 	return ret_mask;
 }
 
diff --git a/drivers/gpu/nvgpu/common/nvlink/nvlink.c b/drivers/gpu/nvgpu/common/nvlink/nvlink.c
index 223c8b704..2145bfe68 100644
--- a/drivers/gpu/nvgpu/common/nvlink/nvlink.c
+++ b/drivers/gpu/nvgpu/common/nvlink/nvlink.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2021, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018-2022, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -310,13 +310,20 @@ exit:
 
 int nvgpu_nvlink_link_early_init(struct gk20a *g)
 {
+	u32 discovered_links;
 	u32 link_id;
 	int ret = 0;
 	/*
 	 * First check the topology and setup connectivity
 	 * HACK: we are only enabling one link for now!!!
 	 */
-	link_id = (u32)(nvgpu_ffs(g->nvlink.discovered_links) - 1UL);
+	discovered_links = nvgpu_ffs(g->nvlink.discovered_links);
+	if (discovered_links == 0) {
+		nvgpu_err(g, "discovered links is 0");
+		return -EINVAL;
+	}
+
+	link_id = (u32)(discovered_links - 1UL);
 	g->nvlink.links[link_id].remote_info.is_connected = true;
 	g->nvlink.links[link_id].remote_info.device_type =
 							nvgpu_nvlink_endp_tegra;
diff --git a/drivers/gpu/nvgpu/common/pmu/boardobj/boardobjgrp.c b/drivers/gpu/nvgpu/common/pmu/boardobj/boardobjgrp.c
index 286ced387..588933d55 100644
--- a/drivers/gpu/nvgpu/common/pmu/boardobj/boardobjgrp.c
+++ b/drivers/gpu/nvgpu/common/pmu/boardobj/boardobjgrp.c
@@ -1,5 +1,5 @@
 /*
-* Copyright (c) 2016-2020, NVIDIA CORPORATION.  All rights reserved.
+* Copyright (c) 2016-2022, NVIDIA CORPORATION.  All rights reserved.
 *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -66,14 +66,16 @@ static int
 obj_insert_final(struct boardobjgrp *pboardobjgrp,
 	struct pmu_board_obj *obj, u8 index)
 {
-	struct gk20a *g = pboardobjgrp->g;
-
-	nvgpu_log_info(g, " ");
+	struct gk20a *g;
 
 	if (pboardobjgrp == NULL) {
 		return -EINVAL;
 	}
 
+	g = pboardobjgrp->g;
+
+	nvgpu_log_info(g, " ");
+
 	if (obj == NULL) {
 		return -EINVAL;
 	}
@@ -448,7 +450,7 @@ static int pmu_set_impl(struct gk20a *g,
 		return -EINVAL;
 	}
 
-	if ((pcmd->buf == NULL) &&
+	if ((pcmd->buf == NULL) ||
 		(pboardobjgrp->pmu.rpc_func_id ==
 		BOARDOBJGRP_GRP_RPC_FUNC_ID_INVALID)) {
 		return -EINVAL;
@@ -511,7 +513,7 @@ pmu_get_status_impl(struct gk20a *g, struct boardobjgrp *pboardobjgrp,
 		return -EINVAL;
 	}
 
-	if ((pcmd->buf == NULL) &&
+	if ((pcmd->buf == NULL) ||
 		(pboardobjgrp->pmu.rpc_func_id ==
 		BOARDOBJGRP_GRP_RPC_FUNC_ID_INVALID)) {
 		return -EINVAL;
diff --git a/drivers/gpu/nvgpu/common/pmu/fw/fw_ver_ops.c b/drivers/gpu/nvgpu/common/pmu/fw/fw_ver_ops.c
index 678565f44..00d13c838 100644
--- a/drivers/gpu/nvgpu/common/pmu/fw/fw_ver_ops.c
+++ b/drivers/gpu/nvgpu/common/pmu/fw/fw_ver_ops.c
@@ -1423,11 +1423,7 @@ int nvgpu_pmu_init_fw_ver_ops(struct gk20a *g,
 				pmu_get_init_msg_sw_mngd_area_off_v5;
 			fw_ops->get_init_msg_sw_mngd_area_size =
 				pmu_get_init_msg_sw_mngd_area_size_v5;
-			if (app_version == APP_VERSION_GV10X) {
-				fw_ops->clk.clk_set_boot_clk = NULL;
-			} else {
-				fw_ops->clk.clk_set_boot_clk = NULL;
-			}
+			fw_ops->clk.clk_set_boot_clk = NULL;
 		} else {
 			fw_ops->get_init_msg_queue_params =
 				pmu_get_init_msg_queue_params_v4;
diff --git a/drivers/gpu/nvgpu/common/pmu/pg/pmu_pg.c b/drivers/gpu/nvgpu/common/pmu/pg/pmu_pg.c
index fca21b6cb..acd0f8681 100644
--- a/drivers/gpu/nvgpu/common/pmu/pg/pmu_pg.c
+++ b/drivers/gpu/nvgpu/common/pmu/pg/pmu_pg.c
@@ -694,8 +694,7 @@ static int pmu_pg_init_powergating(struct gk20a *g, struct nvgpu_pmu *pmu,
 			pg_engine_id++) {
 
 		if ((BIT32(pg_engine_id) & pg_engine_id_list) != 0U) {
-			if (pmu != NULL &&
-				nvgpu_pmu_get_fw_state(g, pmu) ==
+			if (nvgpu_pmu_get_fw_state(g, pmu) ==
 					PMU_FW_STATE_INIT_RECEIVED) {
 				nvgpu_pmu_fw_state_change(g, pmu,
 					PMU_FW_STATE_ELPG_BOOTING, false);
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_pstate.c b/drivers/gpu/nvgpu/common/pmu/pmu_pstate.c
index 3fb993743..108572ede 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmu_pstate.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmu_pstate.c
@@ -1,7 +1,7 @@
 /*
  * general p state infrastructure
  *
- * Copyright (c) 2016-2020, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2022, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -192,6 +192,9 @@ int nvgpu_pmu_pstate_pmu_setup(struct gk20a *g)
 
 	if (g->ops.clk.support_pmgr_domain) {
 		err = pmgr_domain_pmu_setup(g);
+		if (err != 0) {
+			return err;
+		}
 	}
 
 	err = g->ops.clk.perf_pmu_vfe_load(g);
diff --git a/drivers/gpu/nvgpu/common/pmu/therm/therm_dev.c b/drivers/gpu/nvgpu/common/pmu/therm/therm_dev.c
index a1df09d06..80603589d 100644
--- a/drivers/gpu/nvgpu/common/pmu/therm/therm_dev.c
+++ b/drivers/gpu/nvgpu/common/pmu/therm/therm_dev.c
@@ -82,31 +82,28 @@ static struct pmu_board_obj *therm_device_construct(struct gk20a *g,
 	struct therm_device *ptherm_device = NULL;
 	int status = 0;
 
+	if (pmu_board_obj_get_type(pargs) !=
+			NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_GPU) {
+		nvgpu_err(g, "unsupported therm_device class - 0x%x",
+			pmu_board_obj_get_type(pargs));
+		return NULL;
+	}
+
 	ptherm_device = nvgpu_kzalloc(g, sizeof(struct therm_device));
 	if (ptherm_device == NULL) {
 		return NULL;
 	}
 	obj = (struct pmu_board_obj *)(void *)ptherm_device;
 
-	if (pmu_board_obj_get_type(pargs) ==
-			NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_GPU) {
-		status = construct_therm_device_gpu(g, obj, pargs);
-	} else {
-		nvgpu_err(g, "unsupported therm_device class - 0x%x",
-			pmu_board_obj_get_type(pargs));
-		return NULL;
-	}
+	status = construct_therm_device_gpu(g, obj, pargs);
 
-	if(status != 0) {
-		obj = NULL;
+	if (status != 0) {
 		nvgpu_err(g,
 			"could not allocate memory for therm_device");
-		if (obj != NULL) {
-			nvgpu_kfree(g, obj);
-		}
+		nvgpu_kfree(g, obj);
+		obj = NULL;
 	}
 
-
 	return obj;
 }
 
diff --git a/drivers/gpu/nvgpu/common/vgpu/fifo/fifo_vgpu.c b/drivers/gpu/nvgpu/common/vgpu/fifo/fifo_vgpu.c
index d9141d111..3eab6af9c 100644
--- a/drivers/gpu/nvgpu/common/vgpu/fifo/fifo_vgpu.c
+++ b/drivers/gpu/nvgpu/common/vgpu/fifo/fifo_vgpu.c
@@ -1,7 +1,7 @@
 /*
  * Virtualized GPU Fifo
  *
- * Copyright (c) 2014-2021, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2022, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -113,6 +113,11 @@ int vgpu_fifo_isr(struct gk20a *g, struct tegra_vgpu_fifo_intr_info *info)
 	nvgpu_err(g, "fifo intr (%d) on ch %u",
 		info->type, info->chid);
 
+	if (ch == NULL) {
+		nvgpu_err(g, "Invalid channel");
+		return -EINVAL;
+	}
+
 	switch (info->type) {
 	case TEGRA_VGPU_FIFO_INTR_PBDMA:
 		g->ops.channel.set_error_notifier(ch,
diff --git a/drivers/gpu/nvgpu/hal/nvlink/nvlink_gv100.c b/drivers/gpu/nvgpu/hal/nvlink/nvlink_gv100.c
index 9d60f6ef0..c727ab913 100644
--- a/drivers/gpu/nvgpu/hal/nvlink/nvlink_gv100.c
+++ b/drivers/gpu/nvgpu/hal/nvlink/nvlink_gv100.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2021, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018-2022, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -76,9 +76,6 @@ static const char *gv100_device_type_to_str(u32 type)
 	if (type == NVL_DEVICE(ioctrlmif_multicast)) {
 		return "IOCTRLMIF MULTICAST";
 	}
-	if (type == NVL_DEVICE(nvltlc_multicast)) {
-		return "NVLTLC MULTICAST";
-	}
 	return "UNKNOWN";
 }
 
diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c
index 61669f3eb..8acb0b235 100644
--- a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c
+++ b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c
@@ -1,7 +1,7 @@
 /*
  * Tegra GK20A GPU Debugger/Profiler Driver
  *
- * Copyright (c) 2017-2021, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2022, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -2446,13 +2446,13 @@ static int nvgpu_gpu_access_sysmem_gpu_va(struct gk20a *g, u8 cmd, u32 size,
 
 	ret = dma_buf_vmap(dmabuf, &map);
 	cpu_va = ret ? NULL : map.vaddr;
-#else
-	cpu_va = (u8 *)dma_buf_vmap(dmabuf) + offset;
-#endif
 
 	if (!cpu_va) {
 		return -ENOMEM;
 	}
+#else
+	cpu_va = (u8 *)dma_buf_vmap(dmabuf) + offset;
+#endif
 
 	switch (cmd) {
 	case NVGPU_DBG_GPU_IOCTL_ACCESS_GPUVA_CMD_READ:
diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_prof.c b/drivers/gpu/nvgpu/os/linux/ioctl_prof.c
index 14b0a95ee..e97875c3e 100644
--- a/drivers/gpu/nvgpu/os/linux/ioctl_prof.c
+++ b/drivers/gpu/nvgpu/os/linux/ioctl_prof.c
@@ -810,6 +810,7 @@ static int nvgpu_prof_ioctl_vab_reserve(struct nvgpu_profiler_object *prof,
 		sizeof(struct nvgpu_vab_range_checker) *
 		arg->num_range_checkers)) {
 		gk20a_idle(g);
+		nvgpu_kfree(g, ckr);
 		return -EFAULT;
 	}