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gpu: nvgpu: Segregate volt unit members based on their accessibility

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Currently all unit specific private members are inside ucode_volt_inf.h.
This patch moves the members specific to pmuif to ucode_volt_inf.h and
local to volt.h.
Append all unit specific local functions with volt/nvgpu.
Move volt specific rpc handler from g->pmu to g->pmu->volt.

NVGPU-4492

Change-Id: I626e002b3876c6c5330dec4396b7661b986c6119
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2299555
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Abdul Salam
2020-02-25 12:06:28 +05:30
committed by Alex Waterman
parent 7fb3410d72
commit 29d4831780
17 changed files with 266 additions and 224 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
arch/nvgpu-common.yaml
View File

@@ -888,6 +888,7 @@ pmu:
gpu: dgpu
owner: Mahantesh K
sources: [ common/pmu/volt/volt.c,
common/pmu/volt/volt.h,
common/pmu/volt/volt_dev.c,
common/pmu/volt/volt_policy.c,
common/pmu/volt/volt_rail.c,

2
drivers/gpu/nvgpu/common/pmu/clk/clk_vf_point.c
View File

@@ -46,7 +46,7 @@ int nvgpu_clk_domain_volt_to_freq(struct gk20a *g, u8 clkdomain_idx,
(void)memset(&rpc, 0,
sizeof(struct nv_pmu_rpc_clk_domain_35_prog_freq_to_volt));
rpc.volt_rail_idx =
nvgpu_volt_rail_volt_domain_convert_to_idx(g, railidx);
nvgpu_pmu_volt_rail_volt_domain_convert_to_idx(g, railidx);
rpc.clk_domain_idx = clkdomain_idx;
rpc.voltage_type = CTRL_VOLT_DOMAIN_LOGIC;
rpc.input.value = *pvoltuv;

2
drivers/gpu/nvgpu/common/pmu/clk/clk_vin.c
View File

@@ -468,7 +468,7 @@ static int vin_device_init_pmudata_super(struct gk20a *g,
perf_pmu_data->id = pvin_dev->id;
perf_pmu_data->volt_rail_idx =
nvgpu_volt_rail_volt_domain_convert_to_idx(
nvgpu_pmu_volt_rail_volt_domain_convert_to_idx(
g, pvin_dev->volt_domain);
perf_pmu_data->flls_shared_mask = pvin_dev->flls_shared_mask;
perf_pmu_data->por_override_mode = pvin_dev->por_override_mode;

6
drivers/gpu/nvgpu/common/pmu/ipc/pmu_msg.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -558,8 +558,8 @@ static void pmu_rpc_handler(struct gk20a *g, struct pmu_msg *msg,
nvgpu_pmu_perfmon_rpc_handler(g, pmu, &rpc, rpc_payload);
break;
case PMU_UNIT_VOLT:
if (pmu->volt_rpc_handler != NULL) {
pmu->volt_rpc_handler(g, &rpc);
if (pmu->volt->volt_rpc_handler != NULL) {
pmu->volt->volt_rpc_handler(g, &rpc);
}
break;
case PMU_UNIT_CLK:

2
drivers/gpu/nvgpu/common/pmu/perf/change_seq.c
View File

@@ -296,7 +296,7 @@ int nvgpu_pmu_perf_changeseq_set_clks(struct gk20a *g,
}
gpcclk_voltuv += vmargin_uv;
status = nvgpu_volt_get_vmin_vmax_ps35(g, &vmin_uv, &vmax_uv);
status = nvgpu_pmu_volt_get_vmin_vmax_ps35(g, &vmin_uv, &vmax_uv);
if (status != 0) {
nvgpu_pmu_dbg(g, "Get vmin,vmax failed, proceeding with "
"freq_to_volt value");

17
drivers/gpu/nvgpu/common/pmu/perf/ucode_perf_change_seq_inf.h
View File

@@ -40,13 +40,26 @@
#define CTRL_PERF_CHANGE_SEQ_SCRIPT_MAX_PROFILING_THREADS 8
#define CTRL_PERF_CHANGE_SEQ_SCRIPT_VF_SWITCH_MAX_STEPS 13U
struct ctrl_volt_volt_rail_list_item {
u8 rail_idx;
u32 voltage_uv;
u32 voltage_min_noise_unaware_uv;
u32 voltage_offset_uV[2];
};
struct ctrl_volt_volt_rail_list {
u8 num_rails;
struct ctrl_volt_volt_rail_list_item
rails[CTRL_VOLT_VOLT_RAIL_CLIENT_MAX_RAILS];
};
struct ctrl_perf_chage_seq_change_pmu {
u32 seq_id;
};
struct ctrl_perf_change_seq_change {
struct ctrl_clk_clk_domain_list clk_list;
struct ctrl_volt_volt_rail_list_v1 volt_list;
struct ctrl_volt_volt_rail_list volt_list;
u32 pstate_index;
u32 flags;
u32 vf_points_cache_counter;
@@ -162,7 +175,7 @@ struct ctrl_perf_change_seq_pmu_script_step_clks {
struct ctrl_perf_change_seq_pmu_script_step_volt {
struct ctrl_perf_change_seq_pmu_script_step_super super;
struct ctrl_volt_volt_rail_list_v1 volt_list;
struct ctrl_volt_volt_rail_list volt_list;
struct ctrl_clk_vin_sw_override_list vin_sw_override_list;
};

2
drivers/gpu/nvgpu/common/pmu/perf/vfe_equ.c
View File

@@ -917,7 +917,7 @@ int nvgpu_pmu_perf_vfe_get_volt_margin(struct gk20a *g, u32 *vmargin_uv)
int status = 0;
u8 vmargin_idx;
vmargin_idx = nvgpu_volt_get_vmargin_ps35(g);
vmargin_idx = nvgpu_pmu_volt_get_vmargin_ps35(g);
if (vmargin_idx == 0U) {
return 0;
}

91
drivers/gpu/nvgpu/common/pmu/volt/ucode_volt_inf.h
View File

@@ -24,97 +24,6 @@
#include <nvgpu/flcnif_cmn.h>
#include <nvgpu/pmu/pmuif/boardobj.h>
#include <nvgpu/pmu/pmuif/ctrlboardobj.h>
#define CTRL_VOLT_VOLT_RAIL_MAX_RAILS \
CTRL_BOARDOBJGRP_E32_MAX_OBJECTS
#define CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES 0x04U
#define CTRL_VOLT_VOLT_DEV_VID_VSEL_MAX_ENTRIES 0x8U
#define CTRL_VOLT_DOMAIN_INVALID 0x00U
#define CLK_PROG_VFE_ENTRY_SRAM 0x01U
#define NV_PMU_VOLT_VALUE_0V_IN_UV 0U
/*
* Macros for Voltage Domain HAL.
*/
#define CTRL_VOLT_DOMAIN_HAL_GP10X_SINGLE_RAIL 0x00U
/*!
* Special value corresponding to an invalid Voltage Rail Index.
*/
#define CTRL_VOLT_RAIL_INDEX_INVALID \
CTRL_BOARDOBJ_IDX_INVALID
/*!
* Special value corresponding to an invalid Voltage Device Index.
*/
#define CTRL_VOLT_DEVICE_INDEX_INVALID \
CTRL_BOARDOBJ_IDX_INVALID
/*!
* Special value corresponding to an invalid Voltage Policy Index.
*/
#define CTRL_VOLT_POLICY_INDEX_INVALID \
CTRL_BOARDOBJ_IDX_INVALID
enum nv_pmu_pmgr_pwm_source {
NV_PMU_PMGR_PWM_SOURCE_INVALID = 0,
NV_PMU_PMGR_PWM_SOURCE_THERM_VID_PWM_0 = 4,
NV_PMU_PMGR_PWM_SOURCE_THERM_IPC_VMIN_VID_PWM_0 = 13U,
};
/*!
* Macros for Voltage Device Types.
*/
#define CTRL_VOLT_DEVICE_TYPE_INVALID 0x00U
#define CTRL_VOLT_DEVICE_TYPE_PWM 0x03U
/*
* Macros for Volt Device Operation types.
*/
#define CTRL_VOLT_DEVICE_OPERATION_TYPE_INVALID 0x00U
#define CTRL_VOLT_DEVICE_OPERATION_TYPE_DEFAULT 0x01U
#define CTRL_VOLT_VOLT_DEVICE_OPERATION_TYPE_IPC_VMIN 0x04U
/*!
* Macros for Voltage Domains.
*/
#define CTRL_VOLT_DOMAIN_INVALID 0x00U
#define CTRL_VOLT_DOMAIN_LOGIC 0x01U
#define CTRL_VOLT_DOMAIN_SRAM 0x02U
/*!
* Macros for Volt Policy types.
*
* Virtual VOLT_POLICY types are indexed starting from 0xFF.
*/
#define CTRL_VOLT_POLICY_TYPE_INVALID 0x00U
#define CTRL_VOLT_POLICY_TYPE_SINGLE_RAIL 0x01U
#define CTRL_VOLT_POLICY_TYPE_SR_MULTI_STEP 0x02U
#define CTRL_VOLT_POLICY_TYPE_SR_SINGLE_STEP 0x03U
#define CTRL_VOLT_POLICY_TYPE_SINGLE_RAIL_MULTI_STEP 0x04U
#define CTRL_VOLT_POLICY_TYPE_SPLIT_RAIL 0xFEU
#define CTRL_VOLT_POLICY_TYPE_UNKNOWN 0xFFU
/*!
* Macros for Volt Policy Client types.
*/
#define CTRL_VOLT_POLICY_CLIENT_INVALID 0x00U
#define CTRL_VOLT_POLICY_CLIENT_PERF_CORE_VF_SEQ 0x01U
struct ctrl_volt_volt_rail_list_item {
u8 rail_idx;
u32 voltage_uv;
};
struct ctrl_volt_volt_rail_list {
u8 num_rails;
struct ctrl_volt_volt_rail_list_item
rails[CTRL_VOLT_VOLT_RAIL_MAX_RAILS];
};
struct nv_pmu_volt_volt_rail_boardobjgrp_set_header {
struct nv_pmu_boardobjgrp_e32 super;
};

16
drivers/gpu/nvgpu/common/pmu/volt/volt.c
View File

@@ -24,6 +24,7 @@
#include <nvgpu/gk20a.h>
#include <nvgpu/pmu/cmd.h>
#include "volt.h"
#include "volt_rail.h"
#include "volt_dev.h"
#include "volt_policy.h"
@@ -82,6 +83,8 @@ int nvgpu_pmu_volt_sw_setup(struct gk20a *g)
return err;
}
g->pmu->volt->volt_rpc_handler = nvgpu_pmu_volt_rpc_handler;
return 0;
}
@@ -103,12 +106,23 @@ int nvgpu_pmu_volt_init(struct gk20a *g)
return err;
}
g->pmu->volt->volt_metadata = (struct nvgpu_pmu_volt_metadata *)
nvgpu_kzalloc(g, sizeof(struct nvgpu_pmu_volt_metadata));
if (g->pmu->volt->volt_metadata == NULL) {
err = -ENOMEM;
return err;
}
return err;
}
void nvgpu_pmu_volt_deinit(struct gk20a *g)
{
if ((g->pmu != NULL) && (g->pmu->volt != NULL)) {
if (g->pmu == NULL) {
return;
}
if ((g->pmu->volt != NULL) && (g->pmu->volt->volt_metadata != NULL)) {
nvgpu_kfree(g, g->pmu->volt->volt_metadata);
nvgpu_kfree(g, g->pmu->volt);
g->pmu->volt = NULL;
}

140
drivers/gpu/nvgpu/common/pmu/volt/volt.h Normal file
View File

@@ -0,0 +1,140 @@
/*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_VOLT_H
#define NVGPU_VOLT_H
#include <nvgpu/pmu/pmuif/boardobj.h>
#include <nvgpu/pmu/pmuif/ctrlboardobj.h>
#include <nvgpu/boardobjgrp_e32.h>
#define CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES 0x04U
#define CTRL_VOLT_VOLT_RAIL_MAX_RAILS \
CTRL_BOARDOBJGRP_E32_MAX_OBJECTS
#define CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES 0x04U
#define CTRL_VOLT_VOLT_DEV_VID_VSEL_MAX_ENTRIES 0x8U
#define CTRL_VOLT_DOMAIN_INVALID 0x00U
#define CLK_PROG_VFE_ENTRY_SRAM 0x01U
#define NV_PMU_VOLT_VALUE_0V_IN_UV 0U
/*
* Macros for Voltage Domain HAL.
*/
#define CTRL_VOLT_DOMAIN_HAL_GP10X_SINGLE_RAIL 0x00U
/*!
* Special value corresponding to an invalid Voltage Rail Index.
*/
#define CTRL_VOLT_RAIL_INDEX_INVALID \
CTRL_BOARDOBJ_IDX_INVALID
/*!
* Special value corresponding to an invalid Voltage Device Index.
*/
#define CTRL_VOLT_DEVICE_INDEX_INVALID \
CTRL_BOARDOBJ_IDX_INVALID
/*!
* Special value corresponding to an invalid Voltage Policy Index.
*/
#define CTRL_VOLT_POLICY_INDEX_INVALID \
CTRL_BOARDOBJ_IDX_INVALID
enum nv_pmu_pmgr_pwm_source {
NV_PMU_PMGR_PWM_SOURCE_INVALID = 0,
NV_PMU_PMGR_PWM_SOURCE_THERM_VID_PWM_0 = 4,
NV_PMU_PMGR_PWM_SOURCE_THERM_IPC_VMIN_VID_PWM_0 = 13U,
};
/*!
* Macros for Voltage Device Types.
*/
#define CTRL_VOLT_DEVICE_TYPE_INVALID 0x00U
#define CTRL_VOLT_DEVICE_TYPE_PWM 0x03U
/*
* Macros for Volt Device Operation types.
*/
#define CTRL_VOLT_DEVICE_OPERATION_TYPE_INVALID 0x00U
#define CTRL_VOLT_DEVICE_OPERATION_TYPE_DEFAULT 0x01U
#define CTRL_VOLT_VOLT_DEVICE_OPERATION_TYPE_IPC_VMIN 0x04U
/*!
* Macros for Voltage Domains.
*/
#define CTRL_VOLT_DOMAIN_INVALID 0x00U
#define CTRL_VOLT_DOMAIN_LOGIC 0x01U
#define CTRL_VOLT_DOMAIN_SRAM 0x02U
/*!
* Macros for Volt Policy types.
*
* Virtual VOLT_POLICY types are indexed starting from 0xFF.
*/
#define CTRL_VOLT_POLICY_TYPE_INVALID 0x00U
#define CTRL_VOLT_POLICY_TYPE_SINGLE_RAIL 0x01U
#define CTRL_VOLT_POLICY_TYPE_SR_MULTI_STEP 0x02U
#define CTRL_VOLT_POLICY_TYPE_SR_SINGLE_STEP 0x03U
#define CTRL_VOLT_POLICY_TYPE_SINGLE_RAIL_MULTI_STEP 0x04U
#define CTRL_VOLT_POLICY_TYPE_SPLIT_RAIL 0xFEU
#define CTRL_VOLT_POLICY_TYPE_UNKNOWN 0xFFU
/*!
* Macros for Volt Policy Client types.
*/
#define CTRL_VOLT_POLICY_CLIENT_INVALID 0x00U
#define CTRL_VOLT_POLICY_CLIENT_PERF_CORE_VF_SEQ 0x01U
/*!
* metadata of voltage rail functionality.
*/
struct voltage_rail_metadata {
u8 volt_domain_hal;
u8 pct_delta;
u32 ext_rel_delta_uv[CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES];
u8 logic_rail_idx;
u8 sram_rail_idx;
struct boardobjgrp_e32 volt_rails;
};
struct voltage_device_metadata {
struct boardobjgrp_e32 volt_devices;
};
struct voltage_policy_metadata {
struct boardobjgrp_e32 volt_policies;
u8 perf_core_vf_seq_policy_idx;
};
struct nvgpu_pmu_volt_metadata {
struct voltage_rail_metadata volt_rail_metadata;
struct voltage_device_metadata volt_dev_metadata;
struct voltage_policy_metadata volt_policy_metadata;
};
u8 volt_rail_vbios_volt_domain_convert_to_internal
(struct gk20a *g, u8 vbios_volt_domain);
#endif /* NVGPU_VOLT_H */

33
drivers/gpu/nvgpu/common/pmu/volt/volt_dev.c
View File

@@ -33,6 +33,7 @@
#include <nvgpu/pmu/perf.h>
#include <nvgpu/pmu/volt.h>
#include "volt.h"
#include "ucode_volt_inf.h"
#include "volt_dev.h"
#include "volt_rail.h"
@@ -83,7 +84,7 @@ static int volt_device_pmu_data_init_pwm(struct gk20a *g,
return status;
}
static int construct_volt_device(struct gk20a *g,
static int volt_construct_volt_device(struct gk20a *g,
struct boardobj **ppboardobj, size_t size, void *pargs)
{
struct voltage_device *ptmp_dev = (struct voltage_device *)pargs;
@@ -112,7 +113,7 @@ static int construct_volt_device(struct gk20a *g,
return status;
}
static int construct_pwm_volt_device(struct gk20a *g,
static int volt_construct_pwm_volt_device(struct gk20a *g,
struct boardobj **ppboardobj,
size_t size, void *pargs)
{
@@ -122,7 +123,7 @@ static int construct_pwm_volt_device(struct gk20a *g,
struct voltage_device_pwm *pdev = NULL;
int status = 0;
status = construct_volt_device(g, ppboardobj, size, pargs);
status = volt_construct_volt_device(g, ppboardobj, size, pargs);
if (status != 0) {
return status;
}
@@ -181,7 +182,7 @@ static struct voltage_device *volt_volt_device_construct(struct gk20a *g,
struct boardobj *pboard_obj = NULL;
if (BOARDOBJ_GET_TYPE(pargs) == CTRL_VOLT_DEVICE_TYPE_PWM) {
int status = construct_pwm_volt_device(g, &pboard_obj,
int status = volt_construct_pwm_volt_device(g, &pboard_obj,
sizeof(struct voltage_device_pwm), pargs);
if (status != 0) {
nvgpu_err(g,
@@ -256,7 +257,7 @@ static int volt_get_voltage_device_table_1x_psv(struct gk20a *g,
BIOS_GET_FIELD(s32, p_bios_entry->param4,
NV_VBIOS_VDT_1X_ENTRY_PARAM4_PSV_OFFSET_SCALE);
volt_domain = nvgpu_volt_rail_vbios_volt_domain_convert_to_internal(g,
volt_domain = volt_rail_vbios_volt_domain_convert_to_internal(g,
(u8)p_bios_entry->volt_domain);
if (volt_domain == CTRL_VOLT_DOMAIN_INVALID) {
nvgpu_err(g, "invalid voltage domain = %d",
@@ -408,7 +409,7 @@ done:
return status;
}
static int _volt_device_devgrp_pmudata_instget(struct gk20a *g,
static int volt_device_devgrp_pmudata_instget(struct gk20a *g,
struct nv_pmu_boardobjgrp *pmuboardobjgrp,
struct nv_pmu_boardobj **ppboardobjpmudata, u8 idx)
{
@@ -447,9 +448,9 @@ static int volt_device_state_init(struct gk20a *g,
/* Build VOLT_RAIL SW state from VOLT_DEVICE SW state. */
/* If VOLT_RAIL isn't supported, exit. */
if (!BOARDOBJGRP_IS_EMPTY(&g->pmu->volt->
if (!BOARDOBJGRP_IS_EMPTY(&g->pmu->volt->volt_metadata->
volt_rail_metadata.volt_rails.super)) {
rail_idx = nvgpu_volt_rail_volt_domain_convert_to_idx(g,
rail_idx = nvgpu_pmu_volt_rail_volt_domain_convert_to_idx(g,
pvolt_dev->volt_domain);
if (rail_idx == CTRL_BOARDOBJ_IDX_INVALID) {
nvgpu_err(g,
@@ -459,7 +460,7 @@ static int volt_device_state_init(struct gk20a *g,
}
pRail = (struct voltage_rail *)BOARDOBJGRP_OBJ_GET_BY_IDX(
&g->pmu->volt->volt_rail_metadata.volt_rails.super,
&g->pmu->volt->volt_metadata->volt_rail_metadata.volt_rails.super,
rail_idx);
if (pRail == NULL) {
nvgpu_err(g,
@@ -492,7 +493,7 @@ int volt_dev_pmu_setup(struct gk20a *g)
nvgpu_log_info(g, " ");
pboardobjgrp = &g->pmu->volt->volt_dev_metadata.volt_devices.super;
pboardobjgrp = &g->pmu->volt->volt_metadata->volt_dev_metadata.volt_devices.super;
if (!pboardobjgrp->bconstructed) {
return -EINVAL;
@@ -514,7 +515,7 @@ int volt_dev_sw_setup(struct gk20a *g)
nvgpu_log_info(g, " ");
status = nvgpu_boardobjgrp_construct_e32(g,
&g->pmu->volt->volt_dev_metadata.volt_devices);
&g->pmu->volt->volt_metadata->volt_dev_metadata.volt_devices);
if (status != 0) {
nvgpu_err(g,
"error creating boardobjgrp for volt rail, "
@@ -522,12 +523,12 @@ int volt_dev_sw_setup(struct gk20a *g)
goto done;
}
pboardobjgrp = &g->pmu->volt->volt_dev_metadata.volt_devices.super;
pboardobjgrp = &g->pmu->volt->volt_metadata->volt_dev_metadata.volt_devices.super;
pboardobjgrp->pmudatainstget = _volt_device_devgrp_pmudata_instget;
pboardobjgrp->pmudatainstget = volt_device_devgrp_pmudata_instget;
/* Obtain Voltage Rail Table from VBIOS */
status = volt_get_volt_devices_table(g, &g->pmu->volt->
status = volt_get_volt_devices_table(g, &g->pmu->volt->volt_metadata->
volt_dev_metadata);
if (status != 0) {
goto done;
@@ -546,7 +547,7 @@ int volt_dev_sw_setup(struct gk20a *g)
}
/* update calibration to fuse */
BOARDOBJGRP_FOR_EACH(&(g->pmu->volt->volt_dev_metadata.volt_devices.
BOARDOBJGRP_FOR_EACH(&(g->pmu->volt->volt_metadata->volt_dev_metadata.volt_devices.
super),
struct voltage_device *, pvolt_device, i) {
status = volt_device_state_init(g, pvolt_device);
@@ -559,8 +560,6 @@ int volt_dev_sw_setup(struct gk20a *g)
}
}
g->pmu->volt_rpc_handler = nvgpu_pmu_volt_rpc_handler;
done:
nvgpu_log_info(g, " done status %x", status);
return status;

31
drivers/gpu/nvgpu/common/pmu/volt/volt_policy.c
View File

@@ -29,6 +29,7 @@
#include <nvgpu/pmu/clk/clk.h>
#include <nvgpu/pmu/perf.h>
#include "volt.h"
#include "ucode_volt_inf.h"
#include "volt_policy.h"
@@ -38,7 +39,7 @@ static int volt_policy_pmu_data_init_super(struct gk20a *g,
return nvgpu_boardobj_pmu_data_init_super(g, pboardobj, ppmudata);
}
static int construct_volt_policy(struct gk20a *g,
static int volt_construct_volt_policy(struct gk20a *g,
struct boardobj **ppboardobj, size_t size, void *pArgs)
{
struct voltage_policy *pvolt_policy = NULL;
@@ -56,7 +57,7 @@ static int construct_volt_policy(struct gk20a *g,
return status;
}
static int construct_volt_policy_single_rail(struct gk20a *g,
static int volt_construct_volt_policy_single_rail(struct gk20a *g,
struct boardobj **ppboardobj, size_t size, void *pArgs)
{
struct voltage_policy_single_rail *ptmp_policy =
@@ -64,7 +65,7 @@ static int construct_volt_policy_single_rail(struct gk20a *g,
struct voltage_policy_single_rail *pvolt_policy = NULL;
int status = 0;
status = construct_volt_policy(g, ppboardobj, size, pArgs);
status = volt_construct_volt_policy(g, ppboardobj, size, pArgs);
if (status != 0) {
return status;
}
@@ -97,13 +98,13 @@ done:
return status;
}
static int volt_construct_volt_policy_single_rail(struct gk20a *g,
static int volt_construct_volt_policy_single(struct gk20a *g,
struct boardobj **ppboardobj, size_t size, void *pArgs)
{
struct boardobj *pboardobj = NULL;
int status = 0;
status = construct_volt_policy_single_rail(g, ppboardobj, size, pArgs);
status = volt_construct_volt_policy_single_rail(g, ppboardobj, size, pArgs);
if (status != 0x0) {
return status;
}
@@ -147,7 +148,7 @@ static int volt_construct_volt_policy_single_rail_multi_step(struct gk20a *g,
(struct voltage_policy_single_rail_multi_step *)pargs;
int status = 0;
status = construct_volt_policy_single_rail(g, ppboardobj, size, pargs);
status = volt_construct_volt_policy_single_rail(g, ppboardobj, size, pargs);
if (status != 0) {
return status;
}
@@ -186,7 +187,7 @@ static struct voltage_policy *volt_volt_policy_construct(struct gk20a *g, void *
}
break;
case CTRL_VOLT_POLICY_TYPE_SINGLE_RAIL:
status = volt_construct_volt_policy_single_rail(g,
status = volt_construct_volt_policy_single(g,
&pboard_obj,
sizeof(struct voltage_policy_single_rail),
pargs);
@@ -304,7 +305,7 @@ static int volt_get_volt_policy_table(struct gk20a *g,
done:
return status;
}
static int _volt_policy_devgrp_pmudata_instget(struct gk20a *g,
static int volt_policy_devgrp_pmudata_instget(struct gk20a *g,
struct nv_pmu_boardobjgrp *pmuboardobjgrp,
struct nv_pmu_boardobj **ppboardobjpmudata, u8 idx)
{
@@ -326,7 +327,7 @@ static int _volt_policy_devgrp_pmudata_instget(struct gk20a *g,
return 0;
}
static int _volt_policy_grp_pmudatainit_super(struct gk20a *g,
static int volt_policy_grp_pmudatainit_super(struct gk20a *g,
struct boardobjgrp *pboardobjgrp,
struct nv_pmu_boardobjgrp_super *pboardobjgrppmu)
{
@@ -359,7 +360,7 @@ int volt_policy_pmu_setup(struct gk20a *g)
nvgpu_log_info(g, " ");
pboardobjgrp =
&g->pmu->volt->volt_policy_metadata.volt_policies.super;
&g->pmu->volt->volt_metadata->volt_policy_metadata.volt_policies.super;
if (!pboardobjgrp->bconstructed) {
return -EINVAL;
@@ -379,7 +380,7 @@ int volt_policy_sw_setup(struct gk20a *g)
nvgpu_log_info(g, " ");
status = nvgpu_boardobjgrp_construct_e32(g,
&g->pmu->volt->volt_policy_metadata.volt_policies);
&g->pmu->volt->volt_metadata->volt_policy_metadata.volt_policies);
if (status != 0) {
nvgpu_err(g,
"error creating boardobjgrp for volt rail, "
@@ -388,13 +389,13 @@ int volt_policy_sw_setup(struct gk20a *g)
}
pboardobjgrp =
&g->pmu->volt->volt_policy_metadata.volt_policies.super;
&g->pmu->volt->volt_metadata->volt_policy_metadata.volt_policies.super;
pboardobjgrp->pmudatainstget = _volt_policy_devgrp_pmudata_instget;
pboardobjgrp->pmudatainit = _volt_policy_grp_pmudatainit_super;
pboardobjgrp->pmudatainstget = volt_policy_devgrp_pmudata_instget;
pboardobjgrp->pmudatainit = volt_policy_grp_pmudatainit_super;
/* Obtain Voltage Rail Table from VBIOS */
status = volt_get_volt_policy_table(g, &g->pmu->volt->
status = volt_get_volt_policy_table(g, &g->pmu->volt->volt_metadata->
volt_policy_metadata);
if (status != 0) {
goto done;

81
drivers/gpu/nvgpu/common/pmu/volt/volt_rail.c
View File

@@ -30,6 +30,7 @@
#include <nvgpu/pmu/perf.h>
#include <nvgpu/pmu/volt.h>
#include "volt.h"
#include "ucode_volt_inf.h"
#include "volt_rail.h"
@@ -46,7 +47,7 @@ static int volt_rail_state_init(struct gk20a *g,
for (i = 0; i < CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES; i++) {
pvolt_rail->volt_delta_uv[i] = (int)NV_PMU_VOLT_VALUE_0V_IN_UV;
g->pmu->volt->volt_rail_metadata.ext_rel_delta_uv[i] =
g->pmu->volt->volt_metadata->volt_rail_metadata.ext_rel_delta_uv[i] =
NV_PMU_VOLT_VALUE_0V_IN_UV;
}
@@ -102,7 +103,7 @@ static int volt_rail_init_pmudata_super(struct gk20a *g,
for (i = 0; i < CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES; i++) {
rail_pmu_data->volt_delta_uv[i] = prail->volt_delta_uv[i] +
(int)g->pmu->volt->volt_rail_metadata.ext_rel_delta_uv[i];
(int)g->pmu->volt->volt_metadata->volt_rail_metadata.ext_rel_delta_uv[i];
}
status = nvgpu_boardobjgrpmask_export(&prail->volt_dev_mask.super,
@@ -118,7 +119,7 @@ static int volt_rail_init_pmudata_super(struct gk20a *g,
return status;
}
static struct voltage_rail *construct_volt_rail(struct gk20a *g, void *pargs)
static struct voltage_rail *volt_construct_volt_rail(struct gk20a *g, void *pargs)
{
struct boardobj *board_obj_ptr = NULL;
struct voltage_rail *ptemp_rail = (struct voltage_rail *)pargs;
@@ -198,7 +199,7 @@ static int volt_get_volt_rail_table(struct gk20a *g,
nvgpu_memcpy((u8 *)&entry, entry_ptr,
sizeof(struct vbios_voltage_rail_table_1x_entry));
volt_domain = nvgpu_volt_rail_vbios_volt_domain_convert_to_internal(g,
volt_domain = volt_rail_vbios_volt_domain_convert_to_internal(g,
i);
if (volt_domain == CTRL_VOLT_DOMAIN_INVALID) {
continue;
@@ -259,7 +260,7 @@ static int volt_get_volt_rail_table(struct gk20a *g,
CTRL_PMGR_PWR_EQUATION_INDEX_INVALID;
}
prail = construct_volt_rail(g, &rail_type_data);
prail = volt_construct_volt_rail(g, &rail_type_data);
status = boardobjgrp_objinsert(
&pvolt_rail_metadata->volt_rails.super,
@@ -270,7 +271,7 @@ done:
return status;
}
static int _volt_rail_devgrp_pmudata_instget(struct gk20a *g,
static int volt_rail_devgrp_pmudata_instget(struct gk20a *g,
struct nv_pmu_boardobjgrp *pmuboardobjgrp, struct nv_pmu_boardobj
**ppboardobjpmudata, u8 idx)
{
@@ -292,7 +293,7 @@ static int _volt_rail_devgrp_pmudata_instget(struct gk20a *g,
return 0;
}
static int _volt_rail_devgrp_pmustatus_instget(struct gk20a *g,
static int volt_rail_devgrp_pmustatus_instget(struct gk20a *g,
void *pboardobjgrppmu, struct nv_pmu_boardobj_query
**ppboardobjpmustatus, u8 idx)
{
@@ -337,7 +338,7 @@ static int volt_rail_obj_update(struct gk20a *g,
return 0;
}
static int nvgpu_volt_rail_boardobj_grp_get_status(struct gk20a *g)
static int volt_rail_boardobj_grp_get_status(struct gk20a *g)
{
struct boardobjgrp *pboardobjgrp;
struct boardobjgrpmask *pboardobjgrpmask;
@@ -349,8 +350,8 @@ static int nvgpu_volt_rail_boardobj_grp_get_status(struct gk20a *g)
nvgpu_log_info(g, " ");
pboardobjgrp = &g->pmu->volt->volt_rail_metadata.volt_rails.super;
pboardobjgrpmask = &g->pmu->volt->volt_rail_metadata.volt_rails.mask.super;
pboardobjgrp = &g->pmu->volt->volt_metadata->volt_rail_metadata.volt_rails.super;
pboardobjgrpmask = &g->pmu->volt->volt_metadata->volt_rail_metadata.volt_rails.mask.super;
status = pboardobjgrp->pmugetstatus(g, pboardobjgrp, pboardobjgrpmask);
if (status != 0) {
nvgpu_err(g, "err getting boardobjs from pmu");
@@ -386,7 +387,7 @@ int volt_rail_sw_setup(struct gk20a *g)
nvgpu_log_info(g, " ");
status = nvgpu_boardobjgrp_construct_e32(g,
&g->pmu->volt->volt_rail_metadata.volt_rails);
&g->pmu->volt->volt_metadata->volt_rail_metadata.volt_rails);
if (status != 0) {
nvgpu_err(g,
"error creating boardobjgrp for volt rail, "
@@ -394,16 +395,16 @@ int volt_rail_sw_setup(struct gk20a *g)
goto done;
}
pboardobjgrp = &g->pmu->volt->volt_rail_metadata.volt_rails.super;
pboardobjgrp = &g->pmu->volt->volt_metadata->volt_rail_metadata.volt_rails.super;
pboardobjgrp->pmudatainstget = _volt_rail_devgrp_pmudata_instget;
pboardobjgrp->pmustatusinstget = _volt_rail_devgrp_pmustatus_instget;
pboardobjgrp->pmudatainstget = volt_rail_devgrp_pmudata_instget;
pboardobjgrp->pmustatusinstget = volt_rail_devgrp_pmustatus_instget;
g->pmu->volt->volt_rail_metadata.pct_delta =
g->pmu->volt->volt_metadata->volt_rail_metadata.pct_delta =
NV_PMU_VOLT_VALUE_0V_IN_UV;
/* Obtain Voltage Rail Table from VBIOS */
status = volt_get_volt_rail_table(g, &g->pmu->volt->
status = volt_get_volt_rail_table(g, &g->pmu->volt->volt_metadata->
volt_rail_metadata);
if (status != 0) {
goto done;
@@ -422,7 +423,7 @@ int volt_rail_sw_setup(struct gk20a *g)
}
status = BOARDOBJGRP_PMU_CMD_GRP_GET_STATUS_CONSTRUCT(g,
&g->pmu->volt->volt_rail_metadata.volt_rails.super,
&g->pmu->volt->volt_metadata->volt_rail_metadata.volt_rails.super,
volt, VOLT, volt_rail, VOLT_RAIL);
if (status != 0) {
nvgpu_err(g,
@@ -432,7 +433,7 @@ int volt_rail_sw_setup(struct gk20a *g)
}
/* update calibration to fuse */
BOARDOBJGRP_FOR_EACH(&(g->pmu->volt->volt_rail_metadata.
BOARDOBJGRP_FOR_EACH(&(g->pmu->volt->volt_metadata->volt_rail_metadata.
volt_rails.super),
struct voltage_rail *, pvolt_rail, i) {
status = volt_rail_state_init(g, pvolt_rail);
@@ -456,7 +457,7 @@ int volt_rail_pmu_setup(struct gk20a *g)
nvgpu_log_info(g, " ");
pboardobjgrp = &g->pmu->volt->volt_rail_metadata.volt_rails.super;
pboardobjgrp = &g->pmu->volt->volt_metadata->volt_rail_metadata.volt_rails.super;
if (!pboardobjgrp->bconstructed) {
return -EINVAL;
@@ -468,10 +469,10 @@ int volt_rail_pmu_setup(struct gk20a *g)
return status;
}
u8 nvgpu_volt_rail_vbios_volt_domain_convert_to_internal(struct gk20a *g,
u8 volt_rail_vbios_volt_domain_convert_to_internal(struct gk20a *g,
u8 vbios_volt_domain)
{
if (g->pmu->volt->volt_rail_metadata.volt_domain_hal ==
if (g->pmu->volt->volt_metadata->volt_rail_metadata.volt_domain_hal ==
CTRL_VOLT_DOMAIN_HAL_GP10X_SINGLE_RAIL) {
return CTRL_VOLT_DOMAIN_LOGIC;
} else {
@@ -480,17 +481,6 @@ u8 nvgpu_volt_rail_vbios_volt_domain_convert_to_internal(struct gk20a *g,
}
}
u8 nvgpu_volt_rail_volt_domain_convert_to_idx(struct gk20a *g, u8 volt_domain)
{
if (g->pmu->volt->volt_rail_metadata.volt_domain_hal ==
CTRL_VOLT_DOMAIN_HAL_GP10X_SINGLE_RAIL) {
return 0U;
} else {
nvgpu_err(g, "Unsupported volt domain hal");
return CTRL_BOARDOBJ_IDX_INVALID;
}
}
int volt_rail_volt_dev_register(struct gk20a *g, struct voltage_rail
*pvolt_rail, u8 volt_dev_idx, u8 operation_type)
{
@@ -535,7 +525,18 @@ exit:
return status;
}
int nvgpu_volt_get_vmin_vmax_ps35(struct gk20a *g, u32 *vmin_uv, u32 *vmax_uv)
u8 nvgpu_pmu_volt_rail_volt_domain_convert_to_idx(struct gk20a *g, u8 volt_domain)
{
if (g->pmu->volt->volt_metadata->volt_rail_metadata.volt_domain_hal ==
CTRL_VOLT_DOMAIN_HAL_GP10X_SINGLE_RAIL) {
return 0U;
} else {
nvgpu_err(g, "Unsupported volt domain hal");
return CTRL_BOARDOBJ_IDX_INVALID;
}
}
int nvgpu_pmu_volt_get_vmin_vmax_ps35(struct gk20a *g, u32 *vmin_uv, u32 *vmax_uv)
{
struct boardobjgrp *pboardobjgrp;
struct boardobj *pboardobj = NULL;
@@ -543,13 +544,13 @@ int nvgpu_volt_get_vmin_vmax_ps35(struct gk20a *g, u32 *vmin_uv, u32 *vmax_uv)
int status;
u8 index;
status = nvgpu_volt_rail_boardobj_grp_get_status(g);
status = volt_rail_boardobj_grp_get_status(g);
if (status != 0) {
nvgpu_err(g, "Vfe_var get status failed");
return status;
}
pboardobjgrp = &g->pmu->volt->volt_rail_metadata.volt_rails.super;
pboardobjgrp = &g->pmu->volt->volt_metadata->volt_rail_metadata.volt_rails.super;
BOARDOBJGRP_FOR_EACH(pboardobjgrp, struct boardobj*, pboardobj, index) {
volt_rail = (struct voltage_rail *)(void *)pboardobj;
@@ -564,7 +565,7 @@ int nvgpu_volt_get_vmin_vmax_ps35(struct gk20a *g, u32 *vmin_uv, u32 *vmax_uv)
return status;
}
int nvgpu_volt_get_curr_volt_ps35(struct gk20a *g, u32 *vcurr_uv)
int nvgpu_pmu_volt_get_curr_volt_ps35(struct gk20a *g, u32 *vcurr_uv)
{
struct boardobjgrp *pboardobjgrp;
struct boardobj *pboardobj = NULL;
@@ -572,13 +573,13 @@ int nvgpu_volt_get_curr_volt_ps35(struct gk20a *g, u32 *vcurr_uv)
int status;
u8 index;
status = nvgpu_volt_rail_boardobj_grp_get_status(g);
status = volt_rail_boardobj_grp_get_status(g);
if (status != 0) {
nvgpu_err(g, "volt rail get status failed");
return status;
}
pboardobjgrp = &g->pmu->volt->volt_rail_metadata.volt_rails.super;
pboardobjgrp = &g->pmu->volt->volt_metadata->volt_rail_metadata.volt_rails.super;
BOARDOBJGRP_FOR_EACH(pboardobjgrp, struct boardobj*, pboardobj, index) {
volt_rail = (struct voltage_rail *)(void *)pboardobj;
@@ -590,14 +591,14 @@ int nvgpu_volt_get_curr_volt_ps35(struct gk20a *g, u32 *vcurr_uv)
return status;
}
u8 nvgpu_volt_get_vmargin_ps35(struct gk20a *g)
u8 nvgpu_pmu_volt_get_vmargin_ps35(struct gk20a *g)
{
struct boardobjgrp *pboardobjgrp;
struct boardobj *pboardobj = NULL;
struct voltage_rail *volt_rail = NULL;
u8 index, vmargin_uv;
pboardobjgrp = &g->pmu->volt->volt_rail_metadata.volt_rails.super;
pboardobjgrp = &g->pmu->volt->volt_metadata->volt_rail_metadata.volt_rails.super;
BOARDOBJGRP_FOR_EACH(pboardobjgrp, struct boardobj *, pboardobj, index) {
volt_rail = (struct voltage_rail *)(void *)pboardobj;

2
drivers/gpu/nvgpu/include/nvgpu/pmu.h
View File

@@ -307,8 +307,6 @@ struct nvgpu_pmu {
struct nvgpu_pmu_volt *volt;
void (*remove_support)(struct nvgpu_pmu *pmu);
void (*volt_rpc_handler)(struct gk20a *g,
struct nv_pmu_rpc_header *rpc);
void (*therm_rpc_handler)(struct gk20a *g, struct nvgpu_pmu *pmu,
struct nv_pmu_rpc_header *rpc);
#endif

54
drivers/gpu/nvgpu/include/nvgpu/pmu/volt.h
View File

@@ -24,59 +24,25 @@
#define NVGPU_PMU_VOLT_H
#include <nvgpu/types.h>
#include <nvgpu/boardobjgrp_e32.h>
#include <nvgpu/pmu/msg.h>
struct gk20a;
#define CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES 0x04U
struct nvgpu_pmu_volt_metadata;
#define CTRL_VOLT_DOMAIN_LOGIC 0x01U
#define CLK_PROG_VFE_ENTRY_LOGIC 0x00U
#define CTRL_VOLT_VOLT_RAIL_CLIENT_MAX_RAILS 0x04U
/*!
* metadata of voltage rail functionality.
*/
struct voltage_rail_metadata {
u8 volt_domain_hal;
u8 pct_delta;
u32 ext_rel_delta_uv[CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES];
u8 logic_rail_idx;
u8 sram_rail_idx;
struct boardobjgrp_e32 volt_rails;
};
struct voltage_device_metadata {
struct boardobjgrp_e32 volt_devices;
};
struct voltage_policy_metadata {
struct boardobjgrp_e32 volt_policies;
u8 perf_core_vf_seq_policy_idx;
};
struct nvgpu_pmu_volt {
struct voltage_rail_metadata volt_rail_metadata;
struct voltage_device_metadata volt_dev_metadata;
struct voltage_policy_metadata volt_policy_metadata;
};
struct ctrl_volt_volt_rail_list_item_v1 {
u8 rail_idx;
u32 voltage_uv;
u32 voltage_min_noise_unaware_uv;
u32 voltage_offset_uV[2];
struct nvgpu_pmu_volt_metadata *volt_metadata;
void (*volt_rpc_handler)(struct gk20a *g,
struct nv_pmu_rpc_header *rpc);
};
struct ctrl_volt_volt_rail_list_v1 {
u8 num_rails;
struct ctrl_volt_volt_rail_list_item_v1
rails[CTRL_VOLT_VOLT_RAIL_CLIENT_MAX_RAILS];
};
u8 nvgpu_volt_rail_volt_domain_convert_to_idx(struct gk20a *g, u8 volt_domain);
int nvgpu_volt_get_vmin_vmax_ps35(struct gk20a *g, u32 *vmin_uv, u32 *vmax_uv);
u8 nvgpu_volt_get_vmargin_ps35(struct gk20a *g);
u8 nvgpu_volt_rail_vbios_volt_domain_convert_to_internal
(struct gk20a *g, u8 vbios_volt_domain);
int nvgpu_volt_get_curr_volt_ps35(struct gk20a *g, u32 *vcurr_uv);
u8 nvgpu_pmu_volt_rail_volt_domain_convert_to_idx(struct gk20a *g, u8 volt_domain);
int nvgpu_pmu_volt_get_vmin_vmax_ps35(struct gk20a *g, u32 *vmin_uv, u32 *vmax_uv);
u8 nvgpu_pmu_volt_get_vmargin_ps35(struct gk20a *g);
int nvgpu_pmu_volt_get_curr_volt_ps35(struct gk20a *g, u32 *vcurr_uv);
int nvgpu_pmu_volt_sw_setup(struct gk20a *g);
int nvgpu_pmu_volt_pmu_setup(struct gk20a *g);
void nvgpu_pmu_volt_deinit(struct gk20a *g);

8
drivers/gpu/nvgpu/os/linux/debug_volt.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, NVIDIA Corporation. All rights reserved.
* Copyright (c) 2019-2020, NVIDIA Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -25,7 +25,7 @@ static int get_curr_voltage(void *data, u64 *val)
u32 readval;
int err;
err = nvgpu_volt_get_curr_volt_ps35(g, &readval);
err = nvgpu_pmu_volt_get_curr_volt_ps35(g, &readval);
if (!err)
*val = readval;
@@ -39,7 +39,7 @@ static int get_min_voltage(void *data, u64 *val)
u32 minval, maxval;
int err;
err = nvgpu_volt_get_vmin_vmax_ps35(g, &minval, &maxval);
err = nvgpu_pmu_volt_get_vmin_vmax_ps35(g, &minval, &maxval);
if (!err)
*val = minval;
@@ -53,7 +53,7 @@ static int get_max_voltage(void *data, u64 *val)
u32 minval, maxval;
int err;
err = nvgpu_volt_get_vmin_vmax_ps35(g, &minval, &maxval);
err = nvgpu_pmu_volt_get_vmin_vmax_ps35(g, &minval, &maxval);
if (!err)
*val = maxval;

2
drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c
View File

@@ -1447,7 +1447,7 @@ static int nvgpu_gpu_get_voltage(struct gk20a *g,
nvgpu_speculation_barrier();
err = nvgpu_volt_get_curr_volt_ps35(g, &args->voltage);
err = nvgpu_pmu_volt_get_curr_volt_ps35(g, &args->voltage);
if (err) {
return err;
}