From 2a226092a6425a1539b0932e3cc45e47425b0253 Mon Sep 17 00:00:00 2001 From: Antony Clince Alex Date: Wed, 3 Apr 2019 14:31:09 +0530 Subject: [PATCH] gpu: nvgpu: configure ctxsw ucode wdt timeout period At present the ctxsw ucode wdt timeout period is set to maximum. Calculate the wdt count value as per the specified timeout and SYSCLK frequency. Jira NVGPU-1861 Change-Id: Id85abcccb256e69191bd0540aa7980029ddefc85 Signed-off-by: Antony Clince Alex Reviewed-on: https://git-master.nvidia.com/r/2088572 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/clk_arb/clk_arb.c | 6 +++++ .../gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c | 27 +++++++++++++++++-- drivers/gpu/nvgpu/include/nvgpu/gk20a.h | 2 +- 3 files changed, 32 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/nvgpu/common/clk_arb/clk_arb.c b/drivers/gpu/nvgpu/common/clk_arb/clk_arb.c index 01c1a2001..74ffdc090 100644 --- a/drivers/gpu/nvgpu/common/clk_arb/clk_arb.c +++ b/drivers/gpu/nvgpu/common/clk_arb/clk_arb.c @@ -893,7 +893,13 @@ unsigned long nvgpu_clk_measure_freq(struct gk20a *g, u32 api_domain) unsigned long freq = 0UL; switch (api_domain) { + /* + * Incase of iGPU clocks to each parition (GPC, SYS, LTC, XBAR) are + * generated using 1X GPCCLK and hence should be the same. + */ case CTRL_CLK_DOMAIN_GPCCLK: + case CTRL_CLK_DOMAIN_SYSCLK: + case CTRL_CLK_DOMAIN_XBARCLK: freq = g->ops.clk.get_rate(g, CTRL_CLK_DOMAIN_GPCCLK); break; default: diff --git a/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c b/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c index 5b294a640..ea13a04a6 100644 --- a/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c +++ b/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c @@ -25,6 +25,7 @@ #include #include #include +#include #include "gr_falcon_gm20b.h" #include "common/gr/gr_falcon_priv.h" @@ -37,6 +38,8 @@ #define CTXSW_MEM_SCRUBBING_TIMEOUT_MAX_US 1000U #define CTXSW_MEM_SCRUBBING_TIMEOUT_DEFAULT_US 10U +#define CTXSW_WDT_DEFAULT_VALUE 0x7FFFFFFFU + void gm20b_gr_falcon_load_gpccs_dmem(struct gk20a *g, const u32 *ucode_u32_data, u32 ucode_u32_size) { @@ -607,6 +610,8 @@ static int gm20b_gr_falcon_ctx_wait_ucode(struct gk20a *g, u32 mailbox_id, int gm20b_gr_falcon_wait_ctxsw_ready(struct gk20a *g) { int ret; + uint32_t wdt_val = CTXSW_WDT_DEFAULT_VALUE; + unsigned long sysclk_freq_mhz = 0UL; nvgpu_log_fn(g, " "); @@ -625,8 +630,26 @@ int gm20b_gr_falcon_wait_ctxsw_ready(struct gk20a *g) gr_fecs_current_ctx_valid_false_f()); } - nvgpu_writel(g, gr_fecs_ctxsw_mailbox_clear_r(0), 0xffffffffU); - nvgpu_writel(g, gr_fecs_method_data_r(), 0x7fffffff); + if (nvgpu_platform_is_silicon(g)) { + if (g->ops.clk.measure_freq != NULL) { + sysclk_freq_mhz = g->ops.clk.measure_freq(g, + CTRL_CLK_DOMAIN_SYSCLK) / MHZ; + if (sysclk_freq_mhz == 0UL) { + nvgpu_err(g, "failed to get SYSCLK freq"); + + return -1; + } + nvgpu_info(g, "SYSCLK = %lu MHz", sysclk_freq_mhz); + if (g->ctxsw_wdt_period_us != 0U) { + wdt_val = (unsigned int)(sysclk_freq_mhz * + g->ctxsw_wdt_period_us); + } + } + } + + nvgpu_info(g, "configuring ctxsw_ucode wdt = 0x%x", wdt_val); + nvgpu_writel(g, gr_fecs_ctxsw_mailbox_clear_r(0), U32_MAX); + nvgpu_writel(g, gr_fecs_method_data_r(), wdt_val); nvgpu_writel(g, gr_fecs_method_push_r(), gr_fecs_method_push_adr_set_watchdog_timeout_f()); diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index 033e29fa3..7bc6e713d 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -822,7 +822,6 @@ struct gpu_ops { } intr; u32 (*get_ctxsw_checksum_mismatch_mailbox_val)(void); - struct { int (*report_ecc_parity_err)(struct gk20a *g, u32 hw_id, u32 inst, u32 err_id, @@ -2011,6 +2010,7 @@ struct gk20a { unsigned int ch_wdt_init_limit_ms; u32 ctxsw_timeout_period_ms; + u32 ctxsw_wdt_period_us; struct nvgpu_mutex power_lock;