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gpu: nvgpu: NVENC support on TU104

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This patch adds nvenc support for TU104
- Fetch engine/dev info for nvenc
- Falcon NS boot (fw loading) support
- Engine context creation for nvenc
- Skip golden image for multimedia engines
- Avoid subctx for nvenc as it is a non-VEID engine
- Job submission/flow changes for nvenc
- Code refactoring to scale up the support for other multimedia
  engines in future.

Bug 3763551

Change-Id: I03d4e731ebcef456bcc5ce157f3aa39883270dc0
Signed-off-by: Santosh BS <santoshb@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2859416
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Santosh BS
2023-02-16 12:15:18 +00:00
committed by mobile promotions
parent faf6ff3f34
commit 2a865e3aad
49 changed files with 1481 additions and 65 deletions
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20
drivers/gpu/nvgpu/hal/init/hal_tu104.c
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@@ -171,6 +171,7 @@
#include "hal/pmu/pmu_tu104.h"
#include "hal/falcon/falcon_gk20a.h"
#include "hal/nvdec/nvdec_tu104.h"
#include "hal/nvenc/nvenc_tu104.h"
#include "hal/gsp/gsp_tu104.h"
#ifdef CONFIG_NVGPU_DEBUGGER
#include "hal/perf/perf_gv11b.h"
@@ -219,6 +220,7 @@
#include <nvgpu/ce.h>
#include <nvgpu/ce_app.h>
#include <nvgpu/pmu.h>
#include <nvgpu/nvenc.h>
#ifdef CONFIG_NVGPU_LS_PMU
#include <nvgpu/pmu/pmu_pstate.h>
#endif
@@ -787,6 +789,8 @@ static const struct gops_class tu104_ops_gpu_class = {
#ifdef CONFIG_NVGPU_GRAPHICS
.is_valid_gfx = tu104_class_is_valid_gfx,
#endif
.is_valid_multimedia = tu104_class_is_valid_multimedia,
.is_valid_nvenc = tu104_class_is_valid_nvenc,
};
static const struct gops_fb_ecc tu104_ops_fb_ecc = {
@@ -876,6 +880,20 @@ static const struct gops_nvdec tu104_ops_nvdec = {
.falcon_base_addr = tu104_nvdec_falcon_base_addr,
};
static const struct gops_nvenc tu104_ops_nvenc = {
.base_addr = tu104_nvenc_base_addr,
.init = nvgpu_nvenc_sw_init,
.deinit = nvgpu_nvenc_sw_deinit,
.setup_boot_config = tu104_nvenc_setup_boot_config,
.bootstrap = nvgpu_nvenc_falcon_boot,
.halt_engine = tu104_nvenc_halt_engine,
.reset = nvgpu_nvenc_reset,
.set_irq_regs = tu104_nvenc_set_irq_regs,
.interface_enable = tu104_nvenc_interface_enable,
.multimedia_alloc_ctx = nvgpu_multimedia_setup_ctx,
.multimedia_free_ctx = nvgpu_multimedia_free_ctx,
};
static const struct gops_cg tu104_ops_cg = {
.slcg_bus_load_gating_prod = tu104_slcg_bus_load_gating_prod,
.slcg_ce2_load_gating_prod = tu104_slcg_ce2_load_gating_prod,
@@ -1523,6 +1541,7 @@ static const struct gops_falcon tu104_ops_falcon = {
.copy_from_imem = gk20a_falcon_copy_from_imem,
.get_falcon_ctls = gk20a_falcon_get_ctls,
#endif
.load_ucode = gk20a_falcon_load_ucode_dma,
};
#endif
@@ -1718,6 +1737,7 @@ int tu104_init_hal(struct gk20a *g)
gops->fb.ecc = tu104_ops_fb_ecc;
gops->fb.intr = tu104_ops_fb_intr;
gops->nvdec = tu104_ops_nvdec;
gops->nvenc = tu104_ops_nvenc;
gops->cg = tu104_ops_cg;
gops->fifo = tu104_ops_fifo;
gops->engine = tu104_ops_engine;