gpu: nvgpu: bind sched domains as fds

Replace id-based lookup with fd-based lookup when binding a TSG to a
domain. The device node based domain interface naturally provides access
control; this way userspace tools can limit which uid/gid can access
each domain.

Also, explicitly disallow binding channels to a TSG that has no runlist
domain yet. Normally a TSG is in the default domain if nothing else has
been specified, but the default domain can be deleted.

Jira NVGPU-6788

Change-Id: I2af96dfc002367d894eaf0c175006332f790c27f
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2651165
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit

drivers/gpu/nvgpu/common/fifo/tsg.c

@@ -89,6 +89,15 @@ int nvgpu_tsg_bind_channel(struct nvgpu_tsg *tsg, struct nvgpu_channel *ch)
 		return -EINVAL;
 	}
 
+	/*
+	 * This runlist domain is set either by default or in an explicit
+	 * bind. If the default domain has been deleted, explicit bind is
+	 * mandatory.
+	 */
+	if (tsg->rl_domain == NULL) {
+		return -EINVAL;
+	}
+
 	/* cannot bind more channels than MAX channels supported per TSG */
 	nvgpu_rwsem_down_read(&tsg->ch_list_lock);
 	max_ch_per_tsg = g->ops.runlist.get_max_channels_per_tsg();
@@ -155,10 +164,10 @@ int nvgpu_tsg_bind_channel(struct nvgpu_tsg *tsg, struct nvgpu_channel *ch)
 }
 
 #ifdef CONFIG_NVS_PRESENT
-int nvgpu_tsg_bind_domain(struct nvgpu_tsg *tsg, u64 domain_id)
+int nvgpu_tsg_bind_domain(struct nvgpu_tsg *tsg, struct nvgpu_nvs_domain *nnvs_domain)
 {
 	struct nvgpu_runlist_domain *rl_domain;
-	struct nvgpu_nvs_domain *nvs_domain;
+	struct nvs_domain *nvs_domain;
 	struct gk20a *g = tsg->g;
 
 	/* Hopping channels from one domain to another is not allowed */
@@ -166,25 +175,20 @@ int nvgpu_tsg_bind_domain(struct nvgpu_tsg *tsg, u64 domain_id)
 		return -EINVAL;
 	}
 
-	nvs_domain = nvgpu_nvs_domain_by_id(g, domain_id);
+	nvs_domain = nnvs_domain->parent;
-	if (nvs_domain == NULL) {
-		nvgpu_err(g, "nvs domain not found (%llu)", domain_id);
-		return -ENOENT;
-	}
 
 	/*
 	 * The domain ptr will get updated with the right id once the runlist
 	 * gets specified based on the first channel.
 	 */
-	rl_domain = nvgpu_rl_domain_get(g, 0, nvs_domain->parent->name);
+	rl_domain = nvgpu_rl_domain_get(g, 0, nvs_domain->name);
 	if (rl_domain == NULL) {
-		nvgpu_err(g, "rl domain not found (%s)", nvs_domain->parent->name);
+		nvgpu_err(g, "rl domain not found (%s)", nvs_domain->name);
 		/*
 		 * This shouldn't happen because the nvs domain guarantees RL domains.
 		 *
 		 * TODO: query this via the nvs domain.
 		 */
-		nvgpu_nvs_domain_put(g, nvs_domain);
 		return -ENOENT;
 	}
 
@@ -193,8 +197,9 @@ int nvgpu_tsg_bind_domain(struct nvgpu_tsg *tsg, u64 domain_id)
 		nvgpu_nvs_domain_put(g, tsg->nvs_domain);
 	}
 
+	nvgpu_nvs_domain_get(g, nnvs_domain);
 	tsg->rl_domain = rl_domain;
-	tsg->nvs_domain = nvs_domain;
+	tsg->nvs_domain = nnvs_domain;
 
 	return 0;
 }

drivers/gpu/nvgpu/include/nvgpu/tsg.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2021, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2022, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -385,7 +385,7 @@ int nvgpu_tsg_bind_channel(struct nvgpu_tsg *tsg,
  * @brief Bind a TSG to a domain.
  *
  * @param tsg [in]		Pointer to TSG struct.
- * @param domain_id [in]	Domain identifier.
+ * @param nnvs_domain [in]	Pointer to nvgpu nvs domain.
  *
  * Make this TSG participate in the given domain, such that it can only be
  * seen by runlist HW when the domain has been scheduled in.
@@ -394,7 +394,7 @@ int nvgpu_tsg_bind_channel(struct nvgpu_tsg *tsg,
  *
  * @return 0 for successful bind, < 0 for failure.
  */
-int nvgpu_tsg_bind_domain(struct nvgpu_tsg *tsg, u64 domain_id);
+int nvgpu_tsg_bind_domain(struct nvgpu_tsg *tsg, struct nvgpu_nvs_domain *nnvs_domain);
 #endif
 
 /**

drivers/gpu/nvgpu/os/linux/ioctl_tsg.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2021, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2022, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -36,10 +36,12 @@
 #include <nvgpu/nvgpu_init.h>
 #include <nvgpu/grmgr.h>
 #include <nvgpu/ltc.h>
+#include <nvgpu/nvs.h>
 
 #include "platform_gk20a.h"
 #include "ioctl_tsg.h"
 #include "ioctl_channel.h"
+#include "ioctl_nvs.h"
 #include "ioctl.h"
 #include "os_linux.h"
 
@@ -180,6 +182,12 @@ out:
 static int nvgpu_tsg_bind_scheduling_domain(struct nvgpu_tsg *tsg,
 		struct nvgpu_tsg_bind_scheduling_domain_args *args)
 {
+	struct nvgpu_nvs_domain *domain;
+	int err;
+
+	if (args->reserved0 != 0) {
+		return -EINVAL;
+	}
 
 	if (args->reserved[0] != 0) {
 		return -EINVAL;
@@ -197,7 +205,16 @@ static int nvgpu_tsg_bind_scheduling_domain(struct nvgpu_tsg *tsg,
 		return -ENOSYS;
 	}
 
-	return nvgpu_tsg_bind_domain(tsg, args->domain_id);
+	domain = nvgpu_nvs_domain_get_from_file(args->domain_fd);
+	if (domain == NULL) {
+		return -ENOENT;
+	}
+
+	err = nvgpu_tsg_bind_domain(tsg, domain);
+
+	nvgpu_nvs_domain_put(tsg->g, domain);
+
+	return err;
 }
 #endif
 

include/uapi/linux/nvgpu.h

@@ -1,7 +1,7 @@
 /*
  * NVGPU Public Interface Header
  *
- * Copyright (c) 2011-2021, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2011-2022, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -42,7 +42,9 @@ struct nvgpu_tsg_bind_channel_ex_args {
 
 struct nvgpu_tsg_bind_scheduling_domain_args {
 	/* in: id of the domain this tsg will be bound to */
-	__u64 domain_id;
+	__s32 domain_fd;
+	/* Must be set to 0 */
+	__s32 reserved0;
 	/* Must be set to 0 */
 	__u64 reserved[3];
 };