From 2ab61849550f213fde1fe588a4433b7f3830efdf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Konsta=20H=C3=B6ltt=C3=A4?= Date: Wed, 23 Feb 2022 12:11:39 +0200 Subject: [PATCH] gpu: nvgpu: debug dump tsg domain name MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Include the scheduling domain name in the channel debug dump. The domain name of a channel is the domain name of its parent TSG, if any. Copy just the name into the dump info to avoid refcounting concerns. While at it, reword the deterministic flag for less ambiguity. Jira NVGPU-6791 Change-Id: I06041277f938e20f23de9aa419cfffbaa028035e Signed-off-by: Konsta Hölttä Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2673101 Tested-by: mobile promotions Reviewed-by: mobile promotions --- drivers/gpu/nvgpu/common/fifo/channel.c | 20 ++++++++++++++++++-- drivers/gpu/nvgpu/include/nvgpu/channel.h | 1 + 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nvgpu/common/fifo/channel.c b/drivers/gpu/nvgpu/common/fifo/channel.c index fde20ea12..f99bd056b 100644 --- a/drivers/gpu/nvgpu/common/fifo/channel.c +++ b/drivers/gpu/nvgpu/common/fifo/channel.c @@ -66,6 +66,7 @@ #include #include #include +#include #include "channel_wdt.h" #include "channel_worker.h" @@ -2135,13 +2136,14 @@ static void nvgpu_channel_info_debug_dump(struct gk20a *g, */ u32 ver = nvgpu_safe_add_u32(g->params.gpu_arch, g->params.gpu_impl); - gk20a_debug_output(o, "%d-%s, TSG: %u, pid %d, refs: %d%s: ", + gk20a_debug_output(o, "%d-%s, TSG: %u, pid %d, refs: %d, deterministic: %s, domain name: %s", info->chid, g->name, info->tsgid, info->pid, info->refs, - info->deterministic ? ", deterministic" : ""); + info->deterministic ? "yes" : "no", + info->nvs_domain_name); gk20a_debug_output(o, "channel status: %s in use %s %s", info->hw_state.enabled ? "" : "not", info->hw_state.status_string, @@ -2214,6 +2216,8 @@ void nvgpu_channel_debug_dump_all(struct gk20a *g, for (chid = 0U; chid < f->num_channels; chid++) { struct nvgpu_channel *ch = &f->channel[chid]; struct nvgpu_channel_dump_info *info = infos[chid]; + struct nvgpu_tsg *tsg; + const char *domain_name; #ifdef CONFIG_NVGPU_SW_SEMAPHORE struct nvgpu_channel_sync_semaphore *sync_sema; struct nvgpu_hw_semaphore *hw_sema = NULL; @@ -2232,11 +2236,23 @@ void nvgpu_channel_debug_dump_all(struct gk20a *g, continue; } + tsg = nvgpu_tsg_from_ch(ch); info->chid = ch->chid; info->tsgid = ch->tsgid; info->pid = ch->pid; info->refs = nvgpu_atomic_read(&ch->ref_count); info->deterministic = nvgpu_channel_is_deterministic(ch); + if (tsg) { + if (tsg->nvs_domain) { + domain_name = nvgpu_nvs_domain_get_name(tsg->nvs_domain); + } else { + domain_name = "(no domain)"; + } + } else { + domain_name = "(no tsg)"; + } + (void)strncpy(info->nvs_domain_name, domain_name, + sizeof(info->nvs_domain_name) - 1U); #ifdef CONFIG_NVGPU_SW_SEMAPHORE if (hw_sema != NULL) { diff --git a/drivers/gpu/nvgpu/include/nvgpu/channel.h b/drivers/gpu/nvgpu/include/nvgpu/channel.h index 53e346830..694cb0568 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/channel.h +++ b/drivers/gpu/nvgpu/include/nvgpu/channel.h @@ -218,6 +218,7 @@ struct nvgpu_channel_dump_info { u32 next; u64 addr; } sema; + char nvs_domain_name[32]; }; /**