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gpu: nvgpu: fix tex rd coalesce disable logic

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NETLIST_REGIONID_SW_CTX_LOAD writes update gr_gpcs_tpcs_tex_m_dbg2_r to
default value that keeps rd coalesce enabled for LG & SU.

Disable rd coalesce for tex, lg and su after NETLIST_REGIONID_SW_CTX_LOAD
writes during gr init and golden ctx init for it to take effect.

For gr sw method handling, don't update the tex rd coalesce on interrupt
with offset *_SET_RD_COALESCE as we want to keep rd coalescing disabled.

Bug 3881919

Change-Id: Ie7e6616d48f84547ce3380bfa395910b7995c05b
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2857141
(cherry picked from commit b2c8827c65)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2859538
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Ramalingam C <ramalingamc@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Sagar Kamble
2023-02-27 15:44:51 +05:30
committed by mobile promotions
parent 3af0fe510e
commit 2acfb55780
8 changed files with 44 additions and 20 deletions
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6
drivers/gpu/nvgpu/common/gr/obj_ctx.c
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@@ -22,6 +22,7 @@
#include <nvgpu/class.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/errata.h>
#include <nvgpu/log.h>
#include <nvgpu/io.h>
#include <nvgpu/mm.h>
@@ -657,6 +658,11 @@ static int nvgpu_gr_obj_ctx_init_hw_state(struct gk20a *g,
}
nvgpu_log_info(g, "end: netlist: sw_ctx_load: register writes");
if (nvgpu_is_errata_present(g, NVGPU_ERRATA_200314091) &&
(g->ops.gr.init.disable_rd_coalesce != NULL)) {
g->ops.gr.init.disable_rd_coalesce(g);
}
nvgpu_log_info(g, "configure sm_hww_esr_report mask after sw_ctx_load");
g->ops.gr.intr.set_hww_esr_report_mask(g);