diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ltc_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ltc_gm20b.h index cc67e5e2e..08c61e2ec 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ltc_gm20b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ltc_gm20b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2021, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -102,8 +102,8 @@ #define ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(v)\ ((U32(v) & 0x1fU) << 16U) #define ltc_ltcs_ltss_dstg_zbc_index_r() (0x0017e338U) -#define ltc_ltcs_ltss_dstg_zbc_index_address_f(v) ((U32(v) & 0xfU) << 0U) #define ltc_ltcs_ltss_dstg_zbc_index_address_s() (4U) +#define ltc_ltcs_ltss_dstg_zbc_index_address_f(v) ((U32(v) & 0xfU) << 0U) #define ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(i)\ (nvgpu_safe_add_u32(0x0017e33cU, nvgpu_safe_mult_u32((i), 4U))) #define ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v() (0x00000004U) diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h index a3547ea1b..fbbe8cd2a 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2021, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -122,7 +122,7 @@ #define fifo_intr_ctxsw_timeout_engine__size_1_v() (0x00000020U) #define fifo_intr_ctxsw_timeout_engine_pending_v() (0x00000001U) #define fifo_intr_ctxsw_timeout_engine_pending_f(i)\ - ((U32(0x1U) << (0U +((i)*1U)))) + ((U32(0x1U) << (0U + ((i)*1U)))) #define fifo_intr_ctxsw_timeout_info_r(i)\ (nvgpu_safe_add_u32(0x00003200U, nvgpu_safe_mult_u32((i), 4U))) #define fifo_intr_ctxsw_timeout_info__size_1_v() (0x00000004U) diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_ce_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_ce_tu104.h index 5f9d7ee75..2971d626d 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_ce_tu104.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_ce_tu104.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -78,14 +78,14 @@ #define ce_grce_config_r(i)\ (nvgpu_safe_add_u32(0x00104034U, nvgpu_safe_mult_u32((i), 4U))) #define ce_grce_config__size_1_v() (0x00000002U) -#define ce_grce_config_shared_lce_f(v) (((v)&0xfU) << 0U) +#define ce_grce_config_shared_lce_f(v) ((U32(v) & 0xfU) << 0U) #define ce_grce_config_shared_lce_none_f() (0xfU) -#define ce_grce_config_shared_f(v) (((v)&0x1U) << 30U) +#define ce_grce_config_shared_f(v) ((U32(v) & 0x1U) << 30U) #define ce_grce_config_timeslice_short_f() (0x0U) #define ce_grce_config_timeslice_long_f() (0x80000000U) #define ce_pce2lce_config_r(i)\ (nvgpu_safe_add_u32(0x00104040U, nvgpu_safe_mult_u32((i), 4U))) #define ce_pce2lce_config__size_1_v() (0x00000004U) -#define ce_pce2lce_config_pce_assigned_lce_f(v) (((v)&0xfU) << 0U) +#define ce_pce2lce_config_pce_assigned_lce_f(v) ((U32(v) & 0xfU) << 0U) #define ce_pce2lce_config_pce_assigned_lce_none_f() (0xfU) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_fb_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_fb_tu104.h index d9bee3b0d..76db091f3 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_fb_tu104.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_fb_tu104.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -68,16 +68,16 @@ #define fb_fbhub_num_active_ltcs_use_nvlink_peer_m(i)\ (U32(0x1U) << (16U + (i)*1U)) #define fb_fbhub_num_active_ltcs_use_nvlink_peer_v(r, i)\ - (((r) >> (16U + i*1U)) & 0x1U) + (((r) >> (16U + (i)*1U)) & 0x1U) #define fb_fbhub_num_active_ltcs_use_nvlink_peer___size_1_v() (0x00000008U) #define fb_fbhub_num_active_ltcs_use_nvlink_peer___size_1_f(i)\ - ((0x0U << (32U +((i)*1U)))) + ((U32(0x0U) << (16U + ((i)*1U)))) #define fb_fbhub_num_active_ltcs_use_nvlink_peer_enabled_v() (0x00000001U) #define fb_fbhub_num_active_ltcs_use_nvlink_peer_enabled_f(i)\ - ((0x1U << (32U +((i)*1U)))) + ((U32(0x1U) << (16U + ((i)*1U)))) #define fb_fbhub_num_active_ltcs_use_nvlink_peer_disabled_v() (0x00000000U) #define fb_fbhub_num_active_ltcs_use_nvlink_peer_disabled_f(i)\ - ((0x0U << (32U +((i)*1U)))) + ((U32(0x0U) << (16U + ((i)*1U)))) #define fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_f(v)\ ((U32(v) & 0x1U) << 25U) #define fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_m() (U32(0x1U) << 25U) @@ -137,16 +137,16 @@ #define fb_hshub_num_active_ltcs_use_nvlink_peer_m(i)\ (U32(0x1U) << (16U + (i)*1U)) #define fb_hshub_num_active_ltcs_use_nvlink_peer_v(r, i)\ - (((r) >> (16U + i*1U)) & 0x1U) + (((r) >> (16U + (i)*1U)) & 0x1U) #define fb_hshub_num_active_ltcs_use_nvlink_peer___size_1_v() (0x00000008U) #define fb_hshub_num_active_ltcs_use_nvlink_peer___size_1_f(i)\ - ((0x0U << (32U +((i)*1U)))) + ((U32(0x0U) << (16U + ((i)*1U)))) #define fb_hshub_num_active_ltcs_use_nvlink_peer_enabled_v() (0x00000001U) #define fb_hshub_num_active_ltcs_use_nvlink_peer_enabled_f(i)\ - ((0x1U << (32U +((i)*1U)))) + ((U32(0x1U) << (16U + ((i)*1U)))) #define fb_hshub_num_active_ltcs_use_nvlink_peer_disabled_v() (0x00000000U) #define fb_hshub_num_active_ltcs_use_nvlink_peer_disabled_f(i)\ - ((0x0U << (32U +((i)*1U)))) + ((U32(0x0U) << (16U + ((i)*1U)))) #define fb_hshub_num_active_ltcs_hub_sys_atomic_mode_f(v)\ ((U32(v) & 0x1U) << 25U) #define fb_hshub_num_active_ltcs_hub_sys_atomic_mode_m() (U32(0x1U) << 25U) diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_fifo_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_fifo_tu104.h index 7a0763433..b6457ae3d 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_fifo_tu104.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_fifo_tu104.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -112,7 +112,7 @@ #define fifo_intr_pbdma_id_status_f(v, i)\ ((U32(v) & 0x1U) << (0U + (i)*1U)) #define fifo_intr_pbdma_id_status_v(r, i)\ - (((r) >> (0U + i*1U)) & 0x1U) + (((r) >> (0U + (i)*1U)) & 0x1U) #define fifo_intr_pbdma_id_status__size_1_v() (0x0000000cU) #define fifo_intr_runlist_r() (0x00002a00U) #define fifo_fb_timeout_r() (0x00002a04U)