diff --git a/arch/nvgpu-hal-new.yaml b/arch/nvgpu-hal-new.yaml index ab95f35d0..dde3fad78 100644 --- a/arch/nvgpu-hal-new.yaml +++ b/arch/nvgpu-hal-new.yaml @@ -114,7 +114,9 @@ ptimer_fusa: safe: yes owner: Sagar Kamble sources: [ hal/ptimer/ptimer_gk20a_fusa.c, - hal/ptimer/ptimer_gk20a.h ] + hal/ptimer/ptimer_gk20a.h, + hal/ptimer/ptimer_ga10b_fusa.c, + hal/ptimer/ptimer_ga10b.h ] ptimer: safe: no diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 3a84e2c02..b7a3c9d39 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -920,6 +920,7 @@ nvgpu-y += \ hal/fb/intr/fb_intr_ecc_ga10b_fusa.o \ hal/fb/vab/vab_ga10b.o \ hal/priv_ring/priv_ring_ga10b_fusa.o \ + hal/ptimer/ptimer_ga10b_fusa.o \ hal/perf/perf_ga10b.o \ hal/regops/regops_ga10b.o \ hal/regops/allowlist_ga10b.o \ diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources index ba8d107b9..5fe179f40 100644 --- a/drivers/gpu/nvgpu/Makefile.sources +++ b/drivers/gpu/nvgpu/Makefile.sources @@ -821,6 +821,7 @@ srcs += hal/init/hal_ga10b.c \ hal/fb/intr/fb_intr_ga10b_fusa.c \ hal/fb/intr/fb_intr_ecc_ga10b_fusa.c \ hal/priv_ring/priv_ring_ga10b_fusa.c \ + hal/ptimer/ptimer_ga10b_fusa.c \ hal/power_features/cg/ga10b_gating_reglist.c \ hal/therm/therm_ga10b_fusa.c \ hal/ce/ce_ga10b_fusa.c \ diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c index 7fe4196f0..b7bb4b958 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c @@ -118,6 +118,7 @@ #include "hal/ptimer/ptimer_gk20a.h" #include "hal/ptimer/ptimer_gp10b.h" #include "hal/ptimer/ptimer_gv11b.h" +#include "hal/ptimer/ptimer_ga10b.h" #ifdef CONFIG_NVGPU_DEBUGGER #include "hal/regops/regops_ga10b.h" #include "hal/regops/allowlist_ga10b.h" @@ -1555,7 +1556,7 @@ static const struct gops_bus ga10b_ops_bus = { }; static const struct gops_ptimer ga10b_ops_ptimer = { - .isr = gk20a_ptimer_isr, + .isr = ga10b_ptimer_isr, #ifdef CONFIG_NVGPU_IOCTL_NON_FUSA .read_ptimer = gk20a_read_ptimer, .get_timestamps_zipper = nvgpu_get_timestamps_zipper, diff --git a/drivers/gpu/nvgpu/hal/ptimer/ptimer_ga10b.h b/drivers/gpu/nvgpu/hal/ptimer/ptimer_ga10b.h new file mode 100644 index 000000000..45b9796cd --- /dev/null +++ b/drivers/gpu/nvgpu/hal/ptimer/ptimer_ga10b.h @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef PTIMER_GA10B_H +#define PTIMER_GA10B_H + +#include + +struct gk20a; + +void ga10b_ptimer_isr(struct gk20a *g); + +#endif /* PTIMER_GA10B_H */ diff --git a/drivers/gpu/nvgpu/hal/ptimer/ptimer_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/ptimer/ptimer_ga10b_fusa.c new file mode 100644 index 000000000..20fe7a995 --- /dev/null +++ b/drivers/gpu/nvgpu/hal/ptimer/ptimer_ga10b_fusa.c @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include + +#include "ptimer_ga10b.h" + +#include + +void ga10b_ptimer_isr(struct gk20a *g) +{ + u32 save0, save1, fecs_errcode = 0; + u32 error_addr; + + save0 = nvgpu_readl(g, timer_pri_timeout_save_0_r()); + if (timer_pri_timeout_save_0_fecs_tgt_v(save0) != 0U) { + /* + * write & addr fields in timeout_save0 + * might not be reliable + */ + fecs_errcode = nvgpu_readl(g, + timer_pri_timeout_fecs_errcode_r()); + } + + save1 = nvgpu_readl(g, timer_pri_timeout_save_1_r()); + error_addr = timer_pri_timeout_save_0_addr_v(save0) << 2; + nvgpu_err(g, "PRI timeout: ADR 0x%08x " + "%s DATA 0x%08x", + error_addr, + (timer_pri_timeout_save_0_write_v(save0) != 0U) ? + "WRITE" : "READ", save1); + + nvgpu_writel(g, timer_pri_timeout_save_0_r(), 0); + nvgpu_writel(g, timer_pri_timeout_save_1_r(), 0); + + if (fecs_errcode != 0U) { + nvgpu_err(g, "FECS_ERRCODE 0x%08x", fecs_errcode); + if (g->ops.priv_ring.decode_error_code != NULL) { + g->ops.priv_ring.decode_error_code(g, + fecs_errcode); + } + } + + nvgpu_report_err_to_sdl(g, NVGPU_ERR_MODULE_PRI, + GPU_PRI_TIMEOUT_ERROR); +}