From 2b36d309cc28f13fe2fbfec55b493102ae3a9797 Mon Sep 17 00:00:00 2001
From: mkumbar <mkumbar@nvidia.com>
Date: Mon, 16 Dec 2019 14:37:32 +0530
Subject: [PATCH] gpu: nvgpu: acr: update doxygen for acr interfaces

Update doxygen for ACR intefaces.

Change-Id: Iede7be6ab6ba2ad34f564b7142e07f797a172ecf
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2263178
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
---
 .../nvgpu/common/acr/nvgpu_acr_interface.h    | 25 +++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/drivers/gpu/nvgpu/common/acr/nvgpu_acr_interface.h b/drivers/gpu/nvgpu/common/acr/nvgpu_acr_interface.h
index 99f66e93b..449f49937 100644
--- a/drivers/gpu/nvgpu/common/acr/nvgpu_acr_interface.h
+++ b/drivers/gpu/nvgpu/common/acr/nvgpu_acr_interface.h
@@ -24,6 +24,8 @@
 #define NVGPU_ACR_INTERFACE_H
 
 /**
+ * @defgroup NVGPURM_BLOB_CONSTRUCT blob construct
+ *
  * Blob construct interfaces:
  * NVGPU creates LS ucode blob in system/FB's non-WPR memory. LS ucodes
  * will be read from filesystem and added to blob for the detected chip.
@@ -44,6 +46,11 @@
  *    ---------------------------------------------
  */
 
+/**
+ * @ingroup NVGPURM_BLOB_CONSTRUCT
+ */
+/** @{*/
+
 /**
  * Light Secure WPR Content Alignments
  */
@@ -68,6 +75,8 @@
 #define LSF_LSB_HEADER_TOTAL_SIZE_MAX	(\
 	ALIGN_UP(sizeof(struct lsf_lsb_header), LSF_LSB_HEADER_ALIGNMENT))
 
+/** @} */
+
 #ifdef CONFIG_NVGPU_DGPU
 /* Maximum SUB WPR header size */
 #define LSF_SUB_WPR_HEADERS_TOTAL_SIZE_MAX	(ALIGN_UP( \
@@ -103,6 +112,11 @@ enum {
 #define LSF_SHARED_DATA_SUB_WPR_PLAYREADY_SHARED_DATA_SIZE_IN_4K	(0x1U)
 #endif
 
+/**
+ * @ingroup NVGPURM_BLOB_CONSTRUCT
+ */
+/** @{*/
+
 /**
  * Image status updated by ACR HS ucode to know the LS
  * Falcon ucode status.
@@ -335,7 +349,11 @@ struct flcn_bl_dmem_desc {
 	u32 argv;
 };
 
+/** @} */
+
 /**
+ * @defgroup NVGPURM_ACR_HS_LOAD_BOOTSTRAP ACR HS ucode load & bootstrap
+ *
  * ACR HS ucode load & bootstrap interfaces:
  * ACR HS ucode is read from the filesystem based on the chip-id by the ACR
  * unit. Read ACR HS ucode will be update with below structs by patching at
@@ -346,6 +364,11 @@ struct flcn_bl_dmem_desc {
  * starts executing on the falcon.
  */
 
+/**
+ * @ingroup NVGPURM_ACR_HS_LOAD_BOOTSTRAP
+ */
+/** @{*/
+
 /**
  * Supporting maximum of 2 regions.
  * This is needed to pre-allocate space in DMEM
@@ -440,4 +463,6 @@ struct flcn_acr_desc {
 	u32 dummy[4];
 };
 
+/** @} */
+
 #endif /* NVGPU_ACR_INTERFACE_H */