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git://nv-tegra.nvidia.com/linux-nvgpu.git
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gpu: nvgpu: gm20b (un)railgate common clock support
Add support for GPU railgating using common clock framework and Tegra DVFS on k4.4 Bug: 200233943 Change-Id: Ief9afd7a5bf3f447e9b91ab181f26dcefff0a8c8 Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com> Reviewed-on: http://git-master/r/1232290 GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
This commit is contained in:
Peter Boonstoppel
committed by
Bharat Nihalani
Bharat Nihalani
parent
fa6ab1943e
commit
2b593224df
@@ -23,6 +23,7 @@
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#include <uapi/linux/nvgpu.h>
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#include <linux/dma-buf.h>
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#include <linux/nvmap.h>
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#include <linux/reset.h>
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#include <linux/tegra_soctherm.h>
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#include <linux/platform/tegra/clock.h>
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#include <linux/platform/tegra/dvfs.h>
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@@ -47,6 +48,12 @@
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#define MC_CLIENT_GPU 34
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#define PMC_GPU_RG_CNTRL_0 0x2d4
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#ifdef CONFIG_COMMON_CLK
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#define GPU_RAIL_NAME "vdd-gpu"
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#else
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#define GPU_RAIL_NAME "vdd_gpu"
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#endif
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extern struct device tegra_vpr_dev;
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struct gk20a_emc_params {
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@@ -303,23 +310,6 @@ static void gk20a_tegra_calibrate_emc(struct device *dev,
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}
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#ifdef CONFIG_TEGRA_CLK_FRAMEWORK
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/*
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* gk20a_tegra_is_railgated()
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*
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* Check status of gk20a power rail
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*/
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static bool gk20a_tegra_is_railgated(struct device *dev)
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{
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struct gk20a_platform *platform = dev_get_drvdata(dev);
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bool ret = false;
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if (!(platform->is_fmodel))
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ret = !tegra_dvfs_is_rail_up(platform->gpu_rail);
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return ret;
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}
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/*
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* gk20a_tegra_railgate()
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*
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@@ -372,60 +362,6 @@ err_power_off:
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return ret;
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}
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/*
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* gm20b_tegra_railgate()
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*
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* Gate (disable) gm20b power rail
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*/
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static int gm20b_tegra_railgate(struct device *dev)
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{
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struct gk20a_platform *platform = dev_get_drvdata(dev);
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int ret = 0;
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if (platform->is_fmodel ||
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!tegra_dvfs_is_rail_up(platform->gpu_rail))
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return 0;
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tegra_mc_flush(MC_CLIENT_GPU);
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udelay(10);
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/* enable clamp */
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pmc_write(0x1, PMC_GPU_RG_CNTRL_0);
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pmc_read(PMC_GPU_RG_CNTRL_0);
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udelay(10);
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platform->reset_assert(dev);
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udelay(10);
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/*
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* GPCPLL is already disabled before entering this function; reference
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* clocks are enabled until now - disable them just before rail gating
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*/
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clk_disable(platform->clk_reset);
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clk_disable(platform->clk[0]);
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clk_disable(platform->clk[1]);
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udelay(10);
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tegra_soctherm_gpu_tsens_invalidate(1);
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if (tegra_dvfs_is_rail_up(platform->gpu_rail)) {
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ret = tegra_dvfs_rail_power_down(platform->gpu_rail);
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if (ret)
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goto err_power_off;
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} else
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pr_info("No GPU regulator?\n");
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return 0;
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err_power_off:
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gk20a_err(dev, "Could not railgate GPU");
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return ret;
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}
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/*
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* gk20a_tegra_unrailgate()
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@@ -498,6 +434,84 @@ err_clk_on:
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return ret;
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}
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#endif
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#if defined(CONFIG_TEGRA_CLK_FRAMEWORK) || defined(CONFIG_TEGRA_DVFS)
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/*
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* gk20a_tegra_is_railgated()
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*
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* Check status of gk20a power rail
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*/
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static bool gk20a_tegra_is_railgated(struct device *dev)
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{
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struct gk20a_platform *platform = dev_get_drvdata(dev);
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bool ret = false;
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if (!platform->is_fmodel)
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ret = !tegra_dvfs_is_rail_up(platform->gpu_rail);
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return ret;
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}
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/*
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* gm20b_tegra_railgate()
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*
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* Gate (disable) gm20b power rail
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*/
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static int gm20b_tegra_railgate(struct device *dev)
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{
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struct gk20a_platform *platform = dev_get_drvdata(dev);
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int ret = 0;
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if (platform->is_fmodel ||
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!tegra_dvfs_is_rail_up(platform->gpu_rail))
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return 0;
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tegra_mc_flush(MC_CLIENT_GPU);
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udelay(10);
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/* enable clamp */
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pmc_write(0x1, PMC_GPU_RG_CNTRL_0);
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pmc_read(PMC_GPU_RG_CNTRL_0);
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udelay(10);
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platform->reset_assert(dev);
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udelay(10);
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/*
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* GPCPLL is already disabled before entering this function; reference
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* clocks are enabled until now - disable them just before rail gating
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*/
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clk_disable_unprepare(platform->clk_reset);
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clk_disable_unprepare(platform->clk[0]);
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clk_disable_unprepare(platform->clk[1]);
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udelay(10);
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tegra_soctherm_gpu_tsens_invalidate(1);
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if (tegra_dvfs_is_rail_up(platform->gpu_rail)) {
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ret = tegra_dvfs_rail_power_down(platform->gpu_rail);
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if (ret)
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goto err_power_off;
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} else
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pr_info("No GPU regulator?\n");
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return 0;
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err_power_off:
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gk20a_err(dev, "Could not railgate GPU");
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return ret;
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}
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/*
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* gm20b_tegra_unrailgate()
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*
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@@ -514,12 +528,14 @@ static int gm20b_tegra_unrailgate(struct device *dev)
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return 0;
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if (!platform->gpu_rail) {
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platform->gpu_rail = tegra_dvfs_get_rail_by_name("vdd_gpu");
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platform->gpu_rail = tegra_dvfs_get_rail_by_name(GPU_RAIL_NAME);
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if (IS_ERR_OR_NULL(platform->gpu_rail)) {
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WARN(1, "No GPU regulator?\n");
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return -EINVAL;
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}
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#ifdef CONFIG_TEGRA_CLK_FRAMEWORK
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first = true;
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#endif
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}
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ret = tegra_dvfs_rail_power_up(platform->gpu_rail);
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@@ -528,19 +544,27 @@ static int gm20b_tegra_unrailgate(struct device *dev)
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tegra_soctherm_gpu_tsens_invalidate(0);
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if (!platform->clk_reset) {
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platform->clk_reset = clk_get(dev, "gpu_gate");
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if (IS_ERR(platform->clk_reset)) {
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gk20a_err(dev, "fail to get gpu reset clk\n");
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goto err_clk_on;
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}
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}
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if (!first) {
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ret = clk_enable(platform->clk_reset);
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ret = clk_prepare_enable(platform->clk_reset);
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if (ret) {
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gk20a_err(dev, "could not turn on gpu_gate");
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goto err_clk_on;
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}
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ret = clk_enable(platform->clk[0]);
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ret = clk_prepare_enable(platform->clk[0]);
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if (ret) {
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gk20a_err(dev, "could not turn on gpu pll");
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goto err_clk_on;
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}
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ret = clk_enable(platform->clk[1]);
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ret = clk_prepare_enable(platform->clk[1]);
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if (ret) {
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gk20a_err(dev, "could not turn on pwr clock");
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goto err_clk_on;
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@@ -580,13 +604,23 @@ err_clk_on:
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}
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#endif
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static struct {
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char *name;
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unsigned long default_rate;
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} tegra_gk20a_clocks[] = {
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#ifdef CONFIG_TEGRA_CLK_FRAMEWORK
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{"PLLG_ref", UINT_MAX},
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{"pwr", 204000000},
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{"emc", UINT_MAX} };
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{"emc", UINT_MAX},
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#elif defined(CONFIG_COMMON_CLK)
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{"gpu_ref", UINT_MAX},
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{"pll_p_out5", 204000000},
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{"emc", UINT_MAX},
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#endif
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};
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/*
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* gk20a_tegra_get_clocks()
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@@ -653,23 +687,32 @@ static int gk20a_tegra_reset_deassert(struct device *dev)
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return 0;
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}
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#if defined(CONFIG_RESET_CONTROLLER) && defined(CONFIG_COMMON_CLK)
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static int gm20b_tegra_reset_assert(struct device *dev)
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{
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struct gk20a_platform *platform = gk20a_get_platform(dev);
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if (!platform->clk_reset) {
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platform->clk_reset = clk_get(dev, "gpu_gate");
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if (IS_ERR(platform->clk_reset)) {
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gk20a_err(dev, "fail to get gpu reset clk\n");
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return PTR_ERR(platform->clk_reset);
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}
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if (!platform->reset_control) {
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WARN(1, "Reset control not initialized\n");
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return -ENOSYS;
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}
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tegra_periph_reset_assert(platform->clk_reset);
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return 0;
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return reset_control_assert(platform->reset_control);
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}
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static int gm20b_tegra_reset_deassert(struct device *dev)
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{
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struct gk20a_platform *platform = gk20a_get_platform(dev);
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if (!platform->reset_control) {
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WARN(1, "Reset control not initialized\n");
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return -ENOSYS;
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}
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return reset_control_deassert(platform->reset_control);
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}
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#endif
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static void gk20a_tegra_scale_init(struct device *dev)
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{
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struct gk20a_platform *platform = gk20a_get_platform(dev);
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@@ -778,6 +821,10 @@ static int gk20a_tegra_probe(struct device *dev)
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gk20a_tegra_get_clocks(dev);
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#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0))
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pmc = ioremap(TEGRA_PMC_BASE, 4096);
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#endif
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return 0;
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}
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@@ -935,7 +982,7 @@ struct gk20a_platform gm20b_tegra_platform = {
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/* power management callbacks */
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.suspend = gk20a_tegra_suspend,
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#ifdef CONFIG_TEGRA_CLK_FRAMEWORK
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#if defined(CONFIG_TEGRA_CLK_FRAMEWORK) || defined(CONFIG_TEGRA_DVFS)
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.railgate = gm20b_tegra_railgate,
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.unrailgate = gm20b_tegra_unrailgate,
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.is_railgated = gk20a_tegra_is_railgated,
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@@ -944,8 +991,13 @@ struct gk20a_platform gm20b_tegra_platform = {
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.busy = gk20a_tegra_busy,
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.idle = gk20a_tegra_idle,
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#if defined(CONFIG_RESET_CONTROLLER) && defined(CONFIG_COMMON_CLK)
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.reset_assert = gm20b_tegra_reset_assert,
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.reset_deassert = gm20b_tegra_reset_deassert,
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#else
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.reset_assert = gk20a_tegra_reset_assert,
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.reset_deassert = gk20a_tegra_reset_deassert,
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#endif
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#ifdef CONFIG_TEGRA_CLK_FRAMEWORK
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.clk_get_rate = gk20a_get_clk_rate,
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