diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
index 3450bf059..1ba0c5235 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
@@ -25,6 +25,7 @@
 #include <nvgpu/dma.h>
 #include <nvgpu/log.h>
 #include <nvgpu/debug.h>
+#include <nvgpu/enabled.h>
 
 #include "gk20a/gk20a.h"
 #include "gk20a/gr_gk20a.h"
@@ -3574,7 +3575,7 @@ static void gr_gv11b_init_gpc_mmu(struct gk20a *g)
 
 	nvgpu_log_info(g, "initialize gpc mmu");
 
-	if (!g->ops.privsecurity) {
+	if (!nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {
 		/* Bypass MMU check for non-secure boot. For
 		 * secure-boot,this register write has no-effect */
 		gk20a_writel(g, fb_priv_mmu_phy_secure_r(), 0xffffffff);
@@ -3601,9 +3602,11 @@ static void gr_gv11b_init_gpc_mmu(struct gk20a *g)
 			gk20a_readl(g, fb_mmu_debug_rd_r()));
 }
 
-void gv11b_init_gr(struct gpu_ops *gops)
+void gv11b_init_gr(struct gk20a *g)
 {
-	gp10b_init_gr(gops);
+	struct gpu_ops *gops = &g->ops;
+
+	gp10b_init_gr(g);
 	gops->gr.init_preemption_state = NULL;
 	gops->gr.init_fs_state = gr_gv11b_init_fs_state;
 	gops->gr.detect_sm_arch = gr_gv11b_detect_sm_arch;
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h
index 0793dae5a..69148554e 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h
@@ -29,7 +29,7 @@ struct zbc_s_table {
 	u32 ref_cnt;
 };
 
-struct gpu_ops;
+struct gk20a;
 
 enum {
 	VOLTA_CHANNEL_GPFIFO_A  = 0xC36F,
@@ -59,7 +59,7 @@ enum {
 
 #define NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0
 
-void gv11b_init_gr(struct gpu_ops *ops);
+void gv11b_init_gr(struct gk20a *g);
 int gr_gv11b_alloc_buffer(struct vm_gk20a *vm, size_t size,
                         struct nvgpu_mem *mem);
 /*zcull*/
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
index 2c20bd049..3ebeb2055 100644
--- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
@@ -358,16 +358,16 @@ int gv11b_init_hal(struct gk20a *g)
 	gops->get_litter_value = gv11b_ops.get_litter_value;
 
 	/* boot in non-secure modes for time beeing */
-	gops->privsecurity = 0;
+	__nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
 	__nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
 
-	gv11b_init_gr(gops);
+	gv11b_init_gr(g);
 	gv11b_init_fecs_trace_ops(gops);
 	gv11b_init_fb(gops);
 	gv11b_init_ce(gops);
 	gv11b_init_gr_ctx(gops);
 	gv11b_init_mm(gops);
-	gv11b_init_pmu_ops(gops);
+	gv11b_init_pmu_ops(g);
 	gv11b_init_regops(gops);
 	gv11b_init_therm_ops(gops);
 
diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c
index d20b9c1ae..35719dff2 100644
--- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c
@@ -20,6 +20,7 @@
 
 #include <nvgpu/pmu.h>
 #include <nvgpu/falcon.h>
+#include <nvgpu/enabled.h>
 
 #include "gk20a/gk20a.h"
 
@@ -234,9 +235,11 @@ static int gv11b_pg_set_subfeature_mask(struct gk20a *g, u32 pg_engine_id)
 	return 0;
 }
 
-void gv11b_init_pmu_ops(struct gpu_ops *gops)
+void gv11b_init_pmu_ops(struct gk20a *g)
 {
-	gp10b_init_pmu_ops(gops);
+	struct gpu_ops *gops = &g->ops;
+
+	gp10b_init_pmu_ops(g);
 	gops->pmu.pmu_nsbootstrap = gv11b_pmu_bootstrap;
 	gops->pmu.is_pmu_supported = gv11b_is_pmu_supported;
 	gops->pmu.reset_engine = gp106_pmu_engine_reset;
diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.h b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.h
index c99923e77..ce10c4cbe 100644
--- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.h
@@ -1,7 +1,7 @@
 /*
  * GV11B PMU
  *
- * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -16,6 +16,8 @@
 #ifndef __PMU_GV11B_H_
 #define __PMU_GV11B_H_
 
-void gv11b_init_pmu_ops(struct gpu_ops *gops);
+struct gk20a;
+
+void gv11b_init_pmu_ops(struct gk20a *g);
 
 #endif /*__PMU_GV11B_H_*/