From 2bded93b288166cac464c81871bbdf6860c259fb Mon Sep 17 00:00:00 2001 From: Amurthyreddy Date: Mon, 10 Dec 2018 13:50:21 +0530 Subject: [PATCH] gpu: nvgpu: MISRA 10.4 enum fixes MISRA rule 10.4 only allows arithmetic conversions on operands of the same essential type category. Fix violations where an arithmetic conversion is performed on enum and non-enum types. JIRA NVGPU-993 Change-Id: Idaf523d7d3aa85294711b77b34821e729d2e747c Signed-off-by: Amurthyreddy Reviewed-on: https://git-master.nvidia.com/r/1964125 Reviewed-by: svc-mobile-coverity Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Adeel Raza Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gk20a/clk_gk20a.h | 4 ++-- drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 2 +- drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 2 +- drivers/gpu/nvgpu/gm20b/gr_gm20b.h | 12 +++++------- drivers/gpu/nvgpu/gp106/gr_gp106.h | 6 ++---- drivers/gpu/nvgpu/gp10b/gr_gp10b.h | 12 +++++------- drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 10 ++++------ drivers/gpu/nvgpu/include/nvgpu/pmu.h | 4 ++-- drivers/gpu/nvgpu/include/nvgpu/sec2.h | 4 ++-- drivers/gpu/nvgpu/tu104/gr_tu104.h | 10 ++++------ 10 files changed, 28 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/nvgpu/gk20a/clk_gk20a.h b/drivers/gpu/nvgpu/gk20a/clk_gk20a.h index 9a9cb5407..64dab21a5 100644 --- a/drivers/gpu/nvgpu/gk20a/clk_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/clk_gk20a.h @@ -29,7 +29,7 @@ #endif #define GPUFREQ_TABLE_END ~(u32)1 -enum { +enum gpc_pll_id { /* only one PLL for gk20a */ GK20A_GPC_PLL = 0, /* 2 PLL revisions for gm20b */ @@ -53,7 +53,7 @@ struct na_dvfs { }; struct pll { - u32 id; + enum gpc_pll_id id; u32 clk_in; /* KHz */ u32 M; u32 N; diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index d839eeaa7..0466fa17a 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c @@ -322,7 +322,7 @@ int gr_gk20a_ctx_wait_ucode(struct gk20a *g, u32 mailbox_id, { struct nvgpu_timeout timeout; u32 delay = GR_FECS_POLL_INTERVAL; - u32 check = WAIT_UCODE_LOOP; + enum wait_ucode_status check = WAIT_UCODE_LOOP; u32 reg; nvgpu_log_fn(g, " "); diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index 271cca42f..41427f501 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h @@ -103,7 +103,7 @@ enum /*global_ctx_buffer_va */ { NR_GLOBAL_CTX_BUF_VA = 7 }; -enum { +enum wait_ucode_status { WAIT_UCODE_LOOP, WAIT_UCODE_TIMEOUT, WAIT_UCODE_ERROR, diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h index e0c001dac..87e5869c4 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h @@ -28,13 +28,11 @@ struct gk20a; struct nvgpu_warpstate; -enum { - MAXWELL_B = 0xB197, - MAXWELL_COMPUTE_B = 0xB1C0, - KEPLER_INLINE_TO_MEMORY_B= 0xA140, - MAXWELL_DMA_COPY_A = 0xB0B5, - MAXWELL_CHANNEL_GPFIFO_A= 0xB06F, -}; +#define MAXWELL_B 0xB197U +#define MAXWELL_COMPUTE_B 0xB1C0U +#define KEPLER_INLINE_TO_MEMORY_B 0xA140U +#define MAXWELL_DMA_COPY_A 0xB0B5U +#define MAXWELL_CHANNEL_GPFIFO_A 0xB06FU #define NVB197_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc #define NVB197_SET_CIRCULAR_BUFFER_SIZE 0x1280 diff --git a/drivers/gpu/nvgpu/gp106/gr_gp106.h b/drivers/gpu/nvgpu/gp106/gr_gp106.h index 25d581694..20e13e9ed 100644 --- a/drivers/gpu/nvgpu/gp106/gr_gp106.h +++ b/drivers/gpu/nvgpu/gp106/gr_gp106.h @@ -27,10 +27,8 @@ struct gk20a; -enum { - PASCAL_B = 0xC197, - PASCAL_COMPUTE_B = 0xC1C0, -}; +#define PASCAL_B 0xC197U +#define PASCAL_COMPUTE_B 0xC1C0U bool gr_gp106_is_valid_class(struct gk20a *g, u32 class_num); u32 gr_gp106_pagepool_default_size(struct gk20a *g); diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h index d3a589519..623bc1df7 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h @@ -34,13 +34,11 @@ struct zbc_entry; struct nvgpu_preemption_modes_rec; struct gk20a_debug_output; -enum { - PASCAL_CHANNEL_GPFIFO_A = 0xC06F, - PASCAL_A = 0xC097, - PASCAL_COMPUTE_A = 0xC0C0, - PASCAL_DMA_COPY_A = 0xC0B5, - PASCAL_DMA_COPY_B = 0xC1B5, -}; +#define PASCAL_CHANNEL_GPFIFO_A 0xC06FU +#define PASCAL_A 0xC097U +#define PASCAL_COMPUTE_A 0xC0C0U +#define PASCAL_DMA_COPY_A 0xC0B5U +#define PASCAL_DMA_COPY_B 0xC1B5U #define NVC097_SET_GO_IDLE_TIMEOUT 0x022cU #define NVC097_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dcU diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index c3a04142a..df97c9cce 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -48,12 +48,10 @@ struct gr_ctx_desc; struct gr_gk20a_isr_data; struct gk20a_debug_output; -enum { - VOLTA_CHANNEL_GPFIFO_A = 0xC36F, - VOLTA_A = 0xC397, - VOLTA_COMPUTE_A = 0xC3C0, - VOLTA_DMA_COPY_A = 0xC3B5, -}; +#define VOLTA_CHANNEL_GPFIFO_A 0xC36FU +#define VOLTA_A 0xC397U +#define VOLTA_COMPUTE_A 0xC3C0U +#define VOLTA_DMA_COPY_A 0xC3B5U #define NVC397_SET_SHADER_EXCEPTIONS 0x1528U #define NVC397_SET_CIRCULAR_BUFFER_SIZE 0x1280U diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu.h b/drivers/gpu/nvgpu/include/nvgpu/pmu.h index b16a22594..0a7746a8f 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmu.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmu.h @@ -113,7 +113,7 @@ #define GK20A_PMU_DMAIDX_PELPG U32(6) #define GK20A_PMU_DMAIDX_END U32(7) -enum { +enum pmu_seq_state { PMU_SEQ_STATE_FREE = 0, PMU_SEQ_STATE_PENDING, PMU_SEQ_STATE_USED, @@ -274,7 +274,7 @@ struct pmu_mutex { struct pmu_sequence { u8 id; - u32 state; + enum pmu_seq_state state; u32 desc; struct pmu_msg *msg; union { diff --git a/drivers/gpu/nvgpu/include/nvgpu/sec2.h b/drivers/gpu/nvgpu/include/nvgpu/sec2.h index 97f4d471d..2f930a4a9 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/sec2.h +++ b/drivers/gpu/nvgpu/include/nvgpu/sec2.h @@ -46,7 +46,7 @@ #define SEC2_INVALID_SEQ_DESC (~0U) -enum { +enum sec2_seq_state { SEC2_SEQ_STATE_FREE = 0U, SEC2_SEQ_STATE_PENDING, SEC2_SEQ_STATE_USED, @@ -58,7 +58,7 @@ typedef void (*sec2_callback)(struct gk20a *g, struct nv_flcn_msg_sec2 *msg, struct sec2_sequence { u8 id; - u32 state; + enum sec2_seq_state state; u32 desc; struct nv_flcn_msg_sec2 *msg; u8 *out_payload; diff --git a/drivers/gpu/nvgpu/tu104/gr_tu104.h b/drivers/gpu/nvgpu/tu104/gr_tu104.h index 5ac378b56..21b6491bb 100644 --- a/drivers/gpu/nvgpu/tu104/gr_tu104.h +++ b/drivers/gpu/nvgpu/tu104/gr_tu104.h @@ -29,12 +29,10 @@ struct gk20a; struct nvgpu_preemption_modes_rec; struct nvgpu_gr_ctx; -enum { - TURING_CHANNEL_GPFIFO_A = 0xC46F, - TURING_A = 0xC597, - TURING_COMPUTE_A = 0xC5C0, - TURING_DMA_COPY_A = 0xC5B5, -}; +#define TURING_CHANNEL_GPFIFO_A 0xC46FU +#define TURING_A 0xC597U +#define TURING_COMPUTE_A 0xC5C0U +#define TURING_DMA_COPY_A 0xC5B5U #define NVC5C0_SET_SHADER_EXCEPTIONS 0x1528U #define NVC5C0_SET_SKEDCHECK 0x23cU