From 2c379cad0f6a01d07102898b362735a574f3aea8 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Tue, 4 Dec 2018 10:41:19 -0800 Subject: [PATCH] gpu: nvgpu: add handling for ctxsw_intr0 ctxsw_intr0 is triggered by ucode even if it is not enabled by driver. Add handling for processing ctxsw_intr0. fecs mailbox(6) is used to report fecs/gpccs misc error codes. Also dump falcon stats for unhandled fecs intr. Bug 2361571 Bug 200472922 Change-Id: Iefb3c0d46ad1d08db07fd3c08cff91a77835908c Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1966984 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 10 +++++++++- drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 3 +++ drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 3 ++- 3 files changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 8fc001cb1..def43c88f 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c @@ -5133,10 +5133,18 @@ int gk20a_gr_handle_fecs_error(struct gk20a *g, struct channel_gk20a *ch, nvgpu_err(g, "fecs watchdog triggered for channel %u, " "cannot ctxsw anymore !!", chid); g->ops.gr.dump_gr_falcon_stats(g); + } else if ((gr_fecs_intr & + gr_fecs_host_int_status_ctxsw_intr_f(CTXSW_INTR0)) != 0U) { + u32 mailbox_value = gk20a_readl(g, gr_fecs_ctxsw_mailbox_r(6)); + + nvgpu_err(g, "ctxsw intr0 set by ucode, error_code: 0x%08x", + mailbox_value); + ret = -1; } else { nvgpu_err(g, - "fecs error interrupt 0x%08x for channel %u", + "unhandled fecs error interrupt 0x%08x for channel %u", gr_fecs_intr, chid); + g->ops.gr.dump_gr_falcon_stats(g); } gk20a_writel(g, gr_fecs_host_int_clear_r(), gr_fecs_intr); diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index b445c3485..bf4e7785a 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h @@ -66,6 +66,9 @@ #define NVGPU_PREEMPTION_MODE_COMPUTE_CTA BIT32(1) #define NVGPU_PREEMPTION_MODE_COMPUTE_CILP BIT32(2) +#define CTXSW_INTR0 BIT32(0) +#define CTXSW_INTR1 BIT32(1) + struct tsg_gk20a; struct channel_gk20a; struct nvgpu_warpstate; diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index ffefb32b7..d90e4f102 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -1983,7 +1983,8 @@ int gr_gp10b_handle_fecs_error(struct gk20a *g, * INTR1 (bit 1 of the HOST_INT_STATUS_CTXSW_INTR) * indicates that a CILP ctxsw save has finished */ - if ((gr_fecs_intr & gr_fecs_host_int_status_ctxsw_intr_f(2)) != 0U) { + if ((gr_fecs_intr & + gr_fecs_host_int_status_ctxsw_intr_f(CTXSW_INTR1)) != 0U) { nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, "CILP: ctxsw save completed!\n");