From 2c560dce0efd6a15b602a38eea7669f5a20f1a10 Mon Sep 17 00:00:00 2001 From: Sagar Kamble Date: Tue, 30 Nov 2021 07:12:54 +0530 Subject: [PATCH] gpu: nvgpu: ga10x: add missing LTC ECC related registers and fields 1. Registers NV_PLTCG_LTC0_LTS0_DSTG_ECC_REPORT and NV_PLTCG_LTC0_LTS0_DSTG_ECC_ADDRESS are deprecated. Remove them. 2. Define NV_PLTCG_LTC0_LTS0_INTR3 for ga100. 3. Add fields and constants for the register NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS. 4. Add new fields for the register NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_CONTROL. Bug 3446731 Change-Id: I3e41198b7b2e75ff69b5c6193e6fd54efae15752 Signed-off-by: Sagar Kamble Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2633958 Reviewed-by: Antony Clince Alex Reviewed-by: Vijayakumar Subbu Reviewed-by: mobile promotions Tested-by: mobile promotions GVS: Gerrit_Virtual_Submit --- .../include/nvgpu/hw/ga100/hw_ltc_ga100.h | 50 ++++++++++++++++--- .../include/nvgpu/hw/ga10b/hw_ltc_ga10b.h | 44 +++++++++++++++- 2 files changed, 85 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_ltc_ga100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_ltc_ga100.h index 412b6afce..487f26e1c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_ltc_ga100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_ltc_ga100.h @@ -284,11 +284,7 @@ (0x8000000U) #define ltc_ltc0_lts0_intr_r() (0x0014040cU) #define ltc_ltc0_lts0_intr2_r() (0x00140408U) -#define ltc_ltc0_lts0_dstg_ecc_report_r() (0x0014051cU) -#define ltc_ltc0_lts0_dstg_ecc_report_sec_count_m() (U32(0xffU) << 0U) -#define ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(r) (((r) >> 0U) & 0xffU) -#define ltc_ltc0_lts0_dstg_ecc_report_ded_count_m() (U32(0xffU) << 16U) -#define ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(r) (((r) >> 16U) & 0xffU) +#define ltc_ltc0_lts0_intr3_r() (0x00140588U) #define ltc_ltcs_ltss_tstg_cmgmt0_r() (0x0017e2a0U) #define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f() (0x1U) #define ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f() (0x300U) @@ -321,9 +317,32 @@ #define ltc_ltcs_ltss_tstg_set_mgmt_1_plc_recompress_rmw_disabled_f() (0x0U) #define ltc_ltcs_ltss_tstg_set_mgmt_1_plc_recompress_rmw_enabled_f()\ (0x20000000U) -#define ltc_ltc0_lts0_dstg_ecc_address_r() (0x00140520U) -#define ltc_ltc0_lts0_dstg_ecc_address_info_ram_m() (U32(0x1U) << 22U) #define ltc_ltc0_lts0_l2_cache_ecc_address_r() (0x001404fcU) +#define ltc_ltc0_lts0_l2_cache_ecc_address_ram_v(r) (((r) >> 22U) & 0xffU) +#define ltc_ltc0_lts0_l2_cache_ecc_address_ram_dstg_db_clrbe_trlram0_v()\ + (0x00000000U) +#define ltc_ltc0_lts0_l2_cache_ecc_address_ram_dstg_db_clrbe_trlram1_v()\ + (0x00000001U) +#define ltc_ltc0_lts0_l2_cache_ecc_address_ram_dstg_db_clrbe_trlram2_v()\ + (0x00000002U) +#define ltc_ltc0_lts0_l2_cache_ecc_address_ram_dstg_db_clrbe_trlram3_v()\ + (0x00000003U) +#define ltc_ltc0_lts0_l2_cache_ecc_address_ram_dstg_db_clrbe_trlram4_v()\ + (0x00000004U) +#define ltc_ltc0_lts0_l2_cache_ecc_address_ram_dstg_db_clrbe_trlram5_v()\ + (0x00000005U) +#define ltc_ltc0_lts0_l2_cache_ecc_address_ram_dstg_db_clrbe_trlram6_v()\ + (0x00000006U) +#define ltc_ltc0_lts0_l2_cache_ecc_address_ram_dstg_db_clrbe_trlram7_v()\ + (0x00000007U) +#define ltc_ltc0_lts0_l2_cache_ecc_address_ram_dstg_db_bank0_v() (0x00000008U) +#define ltc_ltc0_lts0_l2_cache_ecc_address_ram_dstg_db_bank1_v() (0x00000009U) +#define ltc_ltc0_lts0_l2_cache_ecc_address_ram_dstg_db_bank2_v() (0x0000000aU) +#define ltc_ltc0_lts0_l2_cache_ecc_address_ram_dstg_db_bank3_v() (0x0000000bU) +#define ltc_ltc0_lts0_l2_cache_ecc_address_subunit_v(r) (((r) >> 30U) & 0x3U) +#define ltc_ltc0_lts0_l2_cache_ecc_address_subunit_rstg_v() (0x00000000U) +#define ltc_ltc0_lts0_l2_cache_ecc_address_subunit_tstg_v() (0x00000001U) +#define ltc_ltc0_lts0_l2_cache_ecc_address_subunit_dstg_v() (0x00000002U) #define ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_r() (0x001404f4U) #define ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_s() (16U) #define ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_m()\ @@ -336,6 +355,23 @@ (U32(0xffffU) << 0U) #define ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_v(r)\ (((r) >> 0U) & 0xffffU) +#define ltc_ltc0_lts0_l2_cache_ecc_control_r() (0x001404ecU) +#define ltc_ltc0_lts0_l2_cache_ecc_control_inject_corrected_err_f(v)\ + ((U32(v) & 0x1U) << 4U) +#define ltc_ltc0_lts0_l2_cache_ecc_control_inject_uncorrected_err_f(v)\ + ((U32(v) & 0x1U) << 5U) +#define ltc_ltc0_lts0_l2_cache_ecc_control_inject_corrected_err_rstg_f(v)\ + ((U32(v) & 0x1U) << 6U) +#define ltc_ltc0_lts0_l2_cache_ecc_control_inject_uncorrected_err_rstg_f(v)\ + ((U32(v) & 0x1U) << 7U) +#define ltc_ltc0_lts0_l2_cache_ecc_control_inject_corrected_err_tstg_f(v)\ + ((U32(v) & 0x1U) << 8U) +#define ltc_ltc0_lts0_l2_cache_ecc_control_inject_uncorrected_err_tstg_f(v)\ + ((U32(v) & 0x1U) << 9U) +#define ltc_ltc0_lts0_l2_cache_ecc_control_inject_corrected_err_dstg_f(v)\ + ((U32(v) & 0x1U) << 10U) +#define ltc_ltc0_lts0_l2_cache_ecc_control_inject_uncorrected_err_dstg_f(v)\ + ((U32(v) & 0x1U) << 11U) #define ltc_ltc0_lts0_l2_cache_ecc_status_r() (0x001404f0U) #define ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_rstg_m()\ (U32(0x1U) << 0U) diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_ltc_ga10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_ltc_ga10b.h index 1543a4722..bb8591968 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_ltc_ga10b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_ltc_ga10b.h @@ -345,9 +345,32 @@ #define ltc_ltcs_ltss_tstg_set_mgmt_1_plc_recompress_rmw_disabled_f() (0x0U) #define ltc_ltcs_ltss_tstg_set_mgmt_1_plc_recompress_rmw_enabled_f()\ (0x20000000U) -#define ltc_ltc0_lts0_dstg_ecc_address_r() (0x00140520U) -#define ltc_ltc0_lts0_dstg_ecc_address_info_ram_m() (U32(0x1U) << 22U) #define ltc_ltc0_lts0_l2_cache_ecc_address_r() (0x001404fcU) +#define ltc_ltc0_lts0_l2_cache_ecc_address_ram_v(r) (((r) >> 22U) & 0xffU) +#define ltc_ltc0_lts0_l2_cache_ecc_address_ram_dstg_db_clrbe_trlram0_v()\ + (0x00000000U) +#define ltc_ltc0_lts0_l2_cache_ecc_address_ram_dstg_db_clrbe_trlram1_v()\ + (0x00000001U) +#define ltc_ltc0_lts0_l2_cache_ecc_address_ram_dstg_db_clrbe_trlram2_v()\ + (0x00000002U) +#define ltc_ltc0_lts0_l2_cache_ecc_address_ram_dstg_db_clrbe_trlram3_v()\ + (0x00000003U) +#define ltc_ltc0_lts0_l2_cache_ecc_address_ram_dstg_db_clrbe_trlram4_v()\ + (0x00000004U) +#define ltc_ltc0_lts0_l2_cache_ecc_address_ram_dstg_db_clrbe_trlram5_v()\ + (0x00000005U) +#define ltc_ltc0_lts0_l2_cache_ecc_address_ram_dstg_db_clrbe_trlram6_v()\ + (0x00000006U) +#define ltc_ltc0_lts0_l2_cache_ecc_address_ram_dstg_db_clrbe_trlram7_v()\ + (0x00000007U) +#define ltc_ltc0_lts0_l2_cache_ecc_address_ram_dstg_db_bank0_v() (0x00000008U) +#define ltc_ltc0_lts0_l2_cache_ecc_address_ram_dstg_db_bank1_v() (0x00000009U) +#define ltc_ltc0_lts0_l2_cache_ecc_address_ram_dstg_db_bank2_v() (0x0000000aU) +#define ltc_ltc0_lts0_l2_cache_ecc_address_ram_dstg_db_bank3_v() (0x0000000bU) +#define ltc_ltc0_lts0_l2_cache_ecc_address_subunit_v(r) (((r) >> 30U) & 0x3U) +#define ltc_ltc0_lts0_l2_cache_ecc_address_subunit_rstg_v() (0x00000000U) +#define ltc_ltc0_lts0_l2_cache_ecc_address_subunit_tstg_v() (0x00000001U) +#define ltc_ltc0_lts0_l2_cache_ecc_address_subunit_dstg_v() (0x00000002U) #define ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_r() (0x001404f4U) #define ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_s() (16U) #define ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_v(r)\ @@ -356,6 +379,23 @@ #define ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_s() (16U) #define ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_v(r)\ (((r) >> 0U) & 0xffffU) +#define ltc_ltc0_lts0_l2_cache_ecc_control_r() (0x001404ecU) +#define ltc_ltc0_lts0_l2_cache_ecc_control_inject_corrected_err_f(v)\ + ((U32(v) & 0x1U) << 4U) +#define ltc_ltc0_lts0_l2_cache_ecc_control_inject_uncorrected_err_f(v)\ + ((U32(v) & 0x1U) << 5U) +#define ltc_ltc0_lts0_l2_cache_ecc_control_inject_corrected_err_rstg_f(v)\ + ((U32(v) & 0x1U) << 6U) +#define ltc_ltc0_lts0_l2_cache_ecc_control_inject_uncorrected_err_rstg_f(v)\ + ((U32(v) & 0x1U) << 7U) +#define ltc_ltc0_lts0_l2_cache_ecc_control_inject_corrected_err_tstg_f(v)\ + ((U32(v) & 0x1U) << 8U) +#define ltc_ltc0_lts0_l2_cache_ecc_control_inject_uncorrected_err_tstg_f(v)\ + ((U32(v) & 0x1U) << 9U) +#define ltc_ltc0_lts0_l2_cache_ecc_control_inject_corrected_err_dstg_f(v)\ + ((U32(v) & 0x1U) << 10U) +#define ltc_ltc0_lts0_l2_cache_ecc_control_inject_uncorrected_err_dstg_f(v)\ + ((U32(v) & 0x1U) << 11U) #define ltc_ltc0_lts0_l2_cache_ecc_status_r() (0x001404f0U) #define ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_rstg_m()\ (U32(0x1U) << 0U)